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7cbcb9d46f
On exynos mcpm systems the firmware is hardcoded to jump to an address in SRAM (0x02073000) when secondary CPUs come up. By default the firmware puts a bunch of code at that location. That code expects the kernel to fill in a few slots with addresses that it uses to jump back to the kernel's entry point for secondary CPUs. Originally (on prerelease hardware) this firmware code contained a bunch of workarounds to deal with boot ROM bugs. However on all shipped hardware we simply use this code to redirect to a kernel function for bringing up the CPUs. Let's stop relying on the code provided by the bootloader and just plumb in our own (simple) code jump to the kernel. This has the nice benefit of fixing problems due to the fact that older bootloaders (like the one shipped on the Samsung Chromebook 2) might have put slightly different code into this location. Once suspend/resume is implemented for systems using exynos-mcpm we'll need to make sure we reinstall our fixed up code after resume. ...but that's not anything new since IRAM (and thus the address of the mcpm_entry_point) is lost across suspend/resume anyway. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
359 lines
9.1 KiB
C
359 lines
9.1 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* arch/arm/mach-exynos/mcpm-exynos.c
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*
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* Based on arch/arm/mach-vexpress/dcscb.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/arm-cci.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <asm/mcpm.h>
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#include "regs-pmu.h"
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#include "common.h"
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#define EXYNOS5420_CPUS_PER_CLUSTER 4
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#define EXYNOS5420_NR_CLUSTERS 2
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/*
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* The common v7_exit_coherency_flush API could not be used because of the
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* Erratum 799270 workaround. This macro is the same as the common one (in
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* arch/arm/include/asm/cacheflush.h) except for the erratum handling.
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*/
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#define exynos_v7_exit_coherency_flush(level) \
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asm volatile( \
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"stmfd sp!, {fp, ip}\n\t"\
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"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
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"bic r0, r0, #"__stringify(CR_C)"\n\t" \
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"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
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"isb\n\t"\
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"bl v7_flush_dcache_"__stringify(level)"\n\t" \
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"clrex\n\t"\
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"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
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"bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
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/* Dummy Load of a device register to avoid Erratum 799270 */ \
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"ldr r4, [%0]\n\t" \
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"and r4, r4, #0\n\t" \
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"orr r0, r0, r4\n\t" \
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"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
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"isb\n\t" \
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"dsb\n\t" \
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"ldmfd sp!, {fp, ip}" \
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: \
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: "Ir" (S5P_INFORM0) \
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
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"r9", "r10", "lr", "memory")
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() after its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static int
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cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
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#define exynos_cluster_usecnt(cluster) \
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(cpu_use_count[0][cluster] + \
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cpu_use_count[1][cluster] + \
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cpu_use_count[2][cluster] + \
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cpu_use_count[3][cluster])
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#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
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static int exynos_cluster_power_control(unsigned int cluster, int enable)
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{
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unsigned int tries = 100;
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unsigned int val;
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if (enable) {
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exynos_cluster_power_up(cluster);
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val = S5P_CORE_LOCAL_PWR_EN;
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} else {
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exynos_cluster_power_down(cluster);
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val = 0;
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}
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/* Wait until cluster power control is applied */
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while (tries--) {
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if (exynos_cluster_power_state(cluster) == val)
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return 0;
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cpu_relax();
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}
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pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
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enable ? "on" : "off");
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return -ETIMEDOUT;
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}
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static int exynos_power_up(unsigned int cpu, unsigned int cluster)
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{
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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int err = 0;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS)
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return -EINVAL;
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&exynos_mcpm_lock);
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cpu_use_count[cpu][cluster]++;
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if (cpu_use_count[cpu][cluster] == 1) {
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bool was_cluster_down =
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(exynos_cluster_usecnt(cluster) == 1);
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/*
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* Turn on the cluster (L2/COMMON) and then power on the
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* cores.
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*/
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if (was_cluster_down)
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err = exynos_cluster_power_control(cluster, 1);
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if (!err)
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exynos_cpu_power_up(cpunr);
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else
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exynos_cluster_power_control(cluster, 0);
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} else if (cpu_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&exynos_mcpm_lock);
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local_irq_enable();
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return err;
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}
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/*
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* NOTE: This function requires the stack data to be visible through power down
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* and can only be executed on processors like A15 and A7 that hit the cache
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* with the C bit clear in the SCTLR register.
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*/
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static void exynos_power_down(void)
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{
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unsigned int mpidr, cpu, cluster;
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bool last_man = false, skip_wfi = false;
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unsigned int cpunr;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS);
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__mcpm_cpu_going_down(cpu, cluster);
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arch_spin_lock(&exynos_mcpm_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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cpu_use_count[cpu][cluster]--;
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if (cpu_use_count[cpu][cluster] == 0) {
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exynos_cpu_power_down(cpunr);
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if (exynos_cluster_unused(cluster))
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/* TODO: Turn off the cluster here to save power. */
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last_man = true;
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} else if (cpu_use_count[cpu][cluster] == 1) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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*/
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skip_wfi = true;
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} else {
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BUG();
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}
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&exynos_mcpm_lock);
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3\n\t"
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"isb\n\t"
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"dsb"
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: : "r" (0x400));
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}
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/* Flush all cache levels for this cluster. */
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exynos_v7_exit_coherency_flush(all);
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(mpidr);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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arch_spin_unlock(&exynos_mcpm_lock);
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/* Disable and flush the local CPU cache. */
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exynos_v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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}
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static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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{
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unsigned int tries = 100;
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS);
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/* Wait for the core state to be OFF */
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while (tries--) {
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if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
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if ((exynos_cpu_power_state(cpunr) == 0))
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return 0; /* success: the CPU is halted */
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}
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/* Otherwise, wait and retry: */
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msleep(1);
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}
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return -ETIMEDOUT; /* timeout */
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}
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static const struct mcpm_platform_ops exynos_power_ops = {
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.power_up = exynos_power_up,
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.power_down = exynos_power_down,
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.wait_for_powerdown = exynos_wait_for_powerdown,
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};
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static void __init exynos_mcpm_usage_count_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS);
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cpu_use_count[cpu][cluster] = 1;
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}
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile ("\n"
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"cmp r0, #1\n"
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"bxne lr\n"
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"b cci_enable_port_for_self");
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}
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static const struct of_device_id exynos_dt_mcpm_match[] = {
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{ .compatible = "samsung,exynos5420" },
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{ .compatible = "samsung,exynos5800" },
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{},
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};
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static int __init exynos_mcpm_init(void)
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{
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struct device_node *node;
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void __iomem *ns_sram_base_addr;
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int ret;
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node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
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if (!node)
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return -ENODEV;
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of_node_put(node);
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if (!cci_probed())
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return -ENODEV;
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node = of_find_compatible_node(NULL, NULL,
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"samsung,exynos4210-sysram-ns");
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if (!node)
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return -ENODEV;
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ns_sram_base_addr = of_iomap(node, 0);
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of_node_put(node);
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if (!ns_sram_base_addr) {
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pr_err("failed to map non-secure iRAM base address\n");
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return -ENOMEM;
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}
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/*
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* To increase the stability of KFC reset we need to program
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* the PMU SPARE3 register
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*/
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__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
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exynos_mcpm_usage_count_init();
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ret = mcpm_platform_register(&exynos_power_ops);
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if (!ret)
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ret = mcpm_sync_init(exynos_pm_power_up_setup);
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if (ret) {
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iounmap(ns_sram_base_addr);
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return ret;
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}
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mcpm_smp_set_ops();
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pr_info("Exynos MCPM support installed\n");
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/*
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* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
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* as part of secondary_cpu_start(). Let's redirect it to the
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* mcpm_entry_point().
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*/
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__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
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__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
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__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
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iounmap(ns_sram_base_addr);
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return ret;
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}
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early_initcall(exynos_mcpm_init);
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