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c622b29d1f
In order to use S32C1I instruction on cores with ATOMCTL SR the register must be properly initialized. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* arch/xtensa/include/asm/initialize_mmu.h
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*
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* Initializes MMU:
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*
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* For the new V3 MMU we remap the TLB from virtual == physical
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* to the standard Linux mapping used in earlier MMU's.
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*
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* The the MMU we also support a new configuration register that
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* specifies how the S32C1I instruction operates with the cache
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* controller.
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2008 - 2012 Tensilica, Inc.
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*
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* Marc Gauthier <marc@tensilica.com>
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* Pete Delaney <piet@tensilica.com>
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*/
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#ifndef _XTENSA_INITIALIZE_MMU_H
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#define _XTENSA_INITIALIZE_MMU_H
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#ifdef __ASSEMBLY__
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#define XTENSA_HWVERSION_RC_2009_0 230000
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.macro initialize_mmu
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#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
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/*
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* We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
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* For details see Documentation/xtensa/atomctl.txt
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*/
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#if XCHAL_DCACHE_IS_COHERENT
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movi a3, 0x25 /* For SMP/MX -- internal for writeback,
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* RCW otherwise
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*/
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#else
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movi a3, 0x29 /* non-MX -- Most cores use Std Memory
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* Controlers which usually can't use RCW
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*/
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#endif
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wsr a3, atomctl
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#endif /* XCHAL_HAVE_S32C1I &&
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* (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
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*/
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.endm
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#endif /*__ASSEMBLY__*/
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#endif /* _XTENSA_INITIALIZE_MMU_H */
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