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5be36d22b2
- add platform device resources in board files - add new bfin_sir.h to each machines Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
191 lines
6.6 KiB
C
191 lines
6.6 KiB
C
/*
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* File: include/asm-blackfin/mach-bf548/blackfin.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#define BF548_FAMILY
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#include "bf548.h"
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#include "mem_map.h"
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#include "anomaly.h"
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#ifdef CONFIG_BF542
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#include "defBF542.h"
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#endif
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#ifdef CONFIG_BF544
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#include "defBF544.h"
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#endif
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#ifdef CONFIG_BF547
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#include "defBF547.h"
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#endif
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#ifdef CONFIG_BF548
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#include "defBF548.h"
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#endif
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#ifdef CONFIG_BF549
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#include "defBF549.h"
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#endif
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#if !defined(__ASSEMBLY__)
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#ifdef CONFIG_BF542
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#include "cdefBF542.h"
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#endif
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#ifdef CONFIG_BF544
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#include "cdefBF544.h"
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#endif
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#ifdef CONFIG_BF547
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#include "cdefBF547.h"
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#endif
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#ifdef CONFIG_BF548
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#include "cdefBF548.h"
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#endif
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#ifdef CONFIG_BF549
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#include "cdefBF549.h"
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#endif
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/* UART 1*/
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#define bfin_read_UART_THR() bfin_read_UART1_THR()
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#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
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#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
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#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
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#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
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#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
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#define bfin_read_UART_IER() bfin_read_UART1_IER()
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#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
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#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
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#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
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#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
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#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
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#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
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#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
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#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
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#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
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#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
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#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
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#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
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#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
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#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
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#endif
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/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
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* them in the driver, kernel, etc. */
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/* UART_IIR Register */
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#define STATUS(x) ((x << 1) & 0x06)
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#define STATUS_P1 0x02
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#define STATUS_P0 0x01
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/* UART 0*/
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/* DMA Channnel */
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#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
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#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
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#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
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#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
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#define CH_UART_RX CH_UART1_RX
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#define CH_UART_TX CH_UART1_TX
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/* System Interrupt Controller */
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#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
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#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
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#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
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#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
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#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
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#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
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#define IRQ_UART_RX IRQ_UART1_RX
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#define IRQ_UART_TX IRQ_UART1_TX
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#define IRQ_UART_ERROR IRQ_UART1_ERROR
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/* MMR Registers*/
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#define bfin_read_UART_THR() bfin_read_UART1_THR()
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#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
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#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
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#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
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#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
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#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
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#define bfin_read_UART_IER() bfin_read_UART1_IER()
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#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
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#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
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#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
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#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
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#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
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#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
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#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
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#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
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#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
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#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
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#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
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#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
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#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
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#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
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#define BFIN_UART_THR UART1_THR
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#define BFIN_UART_RBR UART1_RBR
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#define BFIN_UART_DLL UART1_DLL
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#define BFIN_UART_IER UART1_IER
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#define BFIN_UART_DLH UART1_DLH
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#define BFIN_UART_IIR UART1_IIR
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#define BFIN_UART_LCR UART1_LCR
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#define BFIN_UART_MCR UART1_MCR
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#define BFIN_UART_LSR UART1_LSR
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#define BFIN_UART_SCR UART1_SCR
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#define BFIN_UART_GCTL UART1_GCTL
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#define BFIN_UART_NR_PORTS 4
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_GCTL 0x08 /* Global Control Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
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#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
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#define OFFSET_THR 0x28 /* Transmit Holding register */
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#define OFFSET_RBR 0x2C /* Receive Buffer register */
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/* PLL_DIV Masks */
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#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
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#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
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#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
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#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
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#endif
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