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https://github.com/edk2-porting/linux-next.git
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95ffa2438d
some BIOS like to use continus MTRR layout, and X driver can not add
WB entries for graphical cards when 4g or more RAM installed.
the patch will change MTRR to discrete.
mtrr_chunk_size= could be used to have smaller continuous block to hold holes.
default is 256m, could be set according to size of graphics card memory.
mtrr_gran_size= could be used to send smallest mtrr block to avoid run out of MTRRs
v2: fix -1 for UC checking
v3: default to disable, and need use enable_mtrr_cleanup to enable this feature
skip the var state change warning.
remove next_basek in range_to_mtrr()
v4: correct warning mask.
v5: CONFIG_MTRR_SANITIZER
v6: fix 1g, 2g, 512 aligment with extra hole
v7: gran_sizek to prevent running out of MTRRs.
v8: fix hole_basek caculation caused when removing next_basek
gran_sizek using when basek is 0.
need to apply
[PATCH] x86: fix trimming e820 with MTRR holes.
right after this one.
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* local mtrr defines.
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*/
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#include <linux/types.h>
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#include <linux/stddef.h>
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#define MTRRcap_MSR 0x0fe
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#define MTRRdefType_MSR 0x2ff
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define NUM_FIXED_RANGES 88
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#define MAX_VAR_RANGES 256
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#define MTRRfix64K_00000_MSR 0x250
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#define MTRRfix16K_80000_MSR 0x258
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#define MTRRfix16K_A0000_MSR 0x259
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#define MTRRfix4K_C0000_MSR 0x268
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#define MTRRfix4K_C8000_MSR 0x269
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#define MTRRfix4K_D0000_MSR 0x26a
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#define MTRRfix4K_D8000_MSR 0x26b
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#define MTRRfix4K_E0000_MSR 0x26c
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#define MTRRfix4K_E8000_MSR 0x26d
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#define MTRRfix4K_F0000_MSR 0x26e
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#define MTRRfix4K_F8000_MSR 0x26f
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#define MTRR_CHANGE_MASK_FIXED 0x01
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#define MTRR_CHANGE_MASK_VARIABLE 0x02
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#define MTRR_CHANGE_MASK_DEFTYPE 0x04
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/* In the Intel processor's MTRR interface, the MTRR type is always held in
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an 8 bit field: */
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typedef u8 mtrr_type;
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extern unsigned int mtrr_usage_table[MAX_VAR_RANGES];
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struct mtrr_ops {
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u32 vendor;
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u32 use_intel_if;
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// void (*init)(void);
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void (*set)(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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void (*set_all)(void);
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void (*get)(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type);
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int (*get_free_region)(unsigned long base, unsigned long size,
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int replace_reg);
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int (*validate_add_page)(unsigned long base, unsigned long size,
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unsigned int type);
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int (*have_wrcomb)(void);
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};
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extern int generic_get_free_region(unsigned long base, unsigned long size,
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int replace_reg);
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extern int generic_validate_add_page(unsigned long base, unsigned long size,
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unsigned int type);
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extern struct mtrr_ops generic_mtrr_ops;
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extern int positive_have_wrcomb(void);
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/* library functions for processor-specific routines */
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struct set_mtrr_context {
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unsigned long flags;
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unsigned long cr4val;
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u32 deftype_lo;
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u32 deftype_hi;
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u32 ccr3;
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};
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struct mtrr_var_range {
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u32 base_lo;
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u32 base_hi;
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u32 mask_lo;
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u32 mask_hi;
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};
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void set_mtrr_done(struct set_mtrr_context *ctxt);
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
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void fill_mtrr_var_range(unsigned int index,
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u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
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void get_mtrr_state(void);
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extern void set_mtrr_ops(struct mtrr_ops * ops);
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extern u64 size_or_mask, size_and_mask;
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extern struct mtrr_ops * mtrr_if;
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#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
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#define use_intel() (mtrr_if && mtrr_if->use_intel_if == 1)
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extern unsigned int num_var_ranges;
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extern u64 mtrr_tom2;
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void mtrr_state_warn(void);
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const char *mtrr_attrib_to_str(int x);
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void mtrr_wrmsr(unsigned, unsigned, unsigned);
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/* CPU specific mtrr init functions */
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int amd_init_mtrr(void);
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int cyrix_init_mtrr(void);
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int centaur_init_mtrr(void);
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