mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
263 lines
9.7 KiB
C
263 lines
9.7 KiB
C
/*
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* include/asm-v850/v850e_uartb.h -- V850E on-chip `UARTB' UART
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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/* The V850E UARTB is basically a superset of the original V850E UART, but
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even where it's the same, the names and details have changed a bit.
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It's similar enough to use the same driver (v850e_uart.c), but the
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details have been abstracted slightly to do so. */
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#ifndef __V850_V850E_UARTB_H__
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#define __V850_V850E_UARTB_H__
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/* Raw hardware interface. */
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#define V850E_UARTB_BASE_ADDR(n) (0xFFFFFA00 + 0x10 * (n))
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/* Addresses of specific UART control registers for channel N. */
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#define V850E_UARTB_CTL0_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x0)
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#define V850E_UARTB_CTL2_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x2)
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#define V850E_UARTB_STR_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x4)
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#define V850E_UARTB_RX_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x6)
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#define V850E_UARTB_RXAP_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x6)
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#define V850E_UARTB_TX_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0x8)
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#define V850E_UARTB_FIC0_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0xA)
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#define V850E_UARTB_FIC1_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0xB)
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#define V850E_UARTB_FIC2_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0xC)
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#define V850E_UARTB_FIS0_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0xE)
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#define V850E_UARTB_FIS1_ADDR(n) (V850E_UARTB_BASE_ADDR(n) + 0xF)
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/* UARTB control register 0 (general config). */
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#define V850E_UARTB_CTL0(n) (*(volatile u8 *)V850E_UARTB_CTL0_ADDR(n))
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/* Control bits for config registers. */
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#define V850E_UARTB_CTL0_PWR 0x80 /* clock enable */
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#define V850E_UARTB_CTL0_TXE 0x40 /* transmit enable */
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#define V850E_UARTB_CTL0_RXE 0x20 /* receive enable */
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#define V850E_UARTB_CTL0_DIR 0x10 /* */
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#define V850E_UARTB_CTL0_PS1 0x08 /* parity */
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#define V850E_UARTB_CTL0_PS0 0x04 /* parity */
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#define V850E_UARTB_CTL0_CL 0x02 /* char len 1:8bit, 0:7bit */
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#define V850E_UARTB_CTL0_SL 0x01 /* stop bit 1:2bit, 0:1bit */
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#define V850E_UARTB_CTL0_PS_MASK 0x0C /* mask covering parity bits */
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#define V850E_UARTB_CTL0_PS_NONE 0x00 /* no parity */
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#define V850E_UARTB_CTL0_PS_ZERO 0x04 /* zero parity */
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#define V850E_UARTB_CTL0_PS_ODD 0x08 /* odd parity */
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#define V850E_UARTB_CTL0_PS_EVEN 0x0C /* even parity */
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#define V850E_UARTB_CTL0_CL_8 0x02 /* char len 1:8bit, 0:7bit */
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#define V850E_UARTB_CTL0_SL_2 0x01 /* stop bit 1:2bit, 0:1bit */
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/* UARTB control register 2 (clock divider). */
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#define V850E_UARTB_CTL2(n) (*(volatile u16 *)V850E_UARTB_CTL2_ADDR(n))
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#define V850E_UARTB_CTL2_MIN 4
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#define V850E_UARTB_CTL2_MAX 0xFFFF
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/* UARTB serial interface status register. */
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#define V850E_UARTB_STR(n) (*(volatile u8 *)V850E_UARTB_STR_ADDR(n))
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/* Control bits for status registers. */
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#define V850E_UARTB_STR_TSF 0x80 /* UBTX or FIFO exist data */
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#define V850E_UARTB_STR_OVF 0x08 /* overflow error */
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#define V850E_UARTB_STR_PE 0x04 /* parity error */
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#define V850E_UARTB_STR_FE 0x02 /* framing error */
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#define V850E_UARTB_STR_OVE 0x01 /* overrun error */
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/* UARTB receive data register. */
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#define V850E_UARTB_RX(n) (*(volatile u8 *)V850E_UARTB_RX_ADDR(n))
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#define V850E_UARTB_RXAP(n) (*(volatile u16 *)V850E_UARTB_RXAP_ADDR(n))
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/* Control bits for status registers. */
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#define V850E_UARTB_RXAP_PEF 0x0200 /* parity error */
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#define V850E_UARTB_RXAP_FEF 0x0100 /* framing error */
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/* UARTB transmit data register. */
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#define V850E_UARTB_TX(n) (*(volatile u8 *)V850E_UARTB_TX_ADDR(n))
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/* UARTB FIFO control register 0. */
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#define V850E_UARTB_FIC0(n) (*(volatile u8 *)V850E_UARTB_FIC0_ADDR(n))
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/* UARTB FIFO control register 1. */
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#define V850E_UARTB_FIC1(n) (*(volatile u8 *)V850E_UARTB_FIC1_ADDR(n))
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/* UARTB FIFO control register 2. */
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#define V850E_UARTB_FIC2(n) (*(volatile u16 *)V850E_UARTB_FIC2_ADDR(n))
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/* UARTB FIFO status register 0. */
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#define V850E_UARTB_FIS0(n) (*(volatile u8 *)V850E_UARTB_FIS0_ADDR(n))
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/* UARTB FIFO status register 1. */
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#define V850E_UARTB_FIS1(n) (*(volatile u8 *)V850E_UARTB_FIS1_ADDR(n))
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/* Slightly abstract interface used by driver. */
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/* Interrupts used by the UART. */
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/* Received when the most recently transmitted character has been sent. */
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#define V850E_UART_TX_IRQ(chan) IRQ_INTUBTIT (chan)
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/* Received when a new character has been received. */
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#define V850E_UART_RX_IRQ(chan) IRQ_INTUBTIR (chan)
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/* Use by serial driver for information purposes. */
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#define V850E_UART_BASE_ADDR(chan) V850E_UARTB_BASE_ADDR(chan)
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/* UART clock generator interface. */
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/* This type encapsulates a particular uart frequency. */
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typedef u16 v850e_uart_speed_t;
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/* Calculate a uart speed from BAUD for this uart. */
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static inline v850e_uart_speed_t v850e_uart_calc_speed (unsigned baud)
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{
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v850e_uart_speed_t speed;
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/*
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* V850E/ME2 UARTB baud rate is determined by the value of UBCTL2
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* fx = V850E_UARTB_BASE_FREQ = CPU_CLOCK_FREQ/4
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* baud = fx / 2*speed [ speed >= 4 ]
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*/
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speed = V850E_UARTB_CTL2_MIN;
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while (((V850E_UARTB_BASE_FREQ / 2) / speed ) > baud)
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speed++;
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return speed;
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}
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/* Return the current speed of uart channel CHAN. */
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#define v850e_uart_speed(chan) V850E_UARTB_CTL2 (chan)
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/* Set the current speed of uart channel CHAN. */
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#define v850e_uart_set_speed(chan, speed) (V850E_UARTB_CTL2 (chan) = (speed))
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/* Return true if SPEED1 and SPEED2 are the same. */
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#define v850e_uart_speed_eq(speed1, speed2) ((speed1) == (speed2))
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/* Minimum baud rate possible. */
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#define v850e_uart_min_baud() \
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((V850E_UARTB_BASE_FREQ / 2) / V850E_UARTB_CTL2_MAX)
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/* Maximum baud rate possible. The error is quite high at max, though. */
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#define v850e_uart_max_baud() \
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((V850E_UARTB_BASE_FREQ / 2) / V850E_UARTB_CTL2_MIN)
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/* The `maximum' clock rate the uart can used, which is wanted (though not
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really used in any useful way) by the serial framework. */
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#define v850e_uart_max_clock() \
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(V850E_UARTB_BASE_FREQ / 2)
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/* UART configuration interface. */
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/* Type of the uart config register; must be a scalar. */
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typedef u16 v850e_uart_config_t;
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/* The uart hardware config register for channel CHAN. */
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#define V850E_UART_CONFIG(chan) V850E_UARTB_CTL0 (chan)
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/* This config bit set if the uart is enabled. */
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#define V850E_UART_CONFIG_ENABLED V850E_UARTB_CTL0_PWR
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/* If the uart _isn't_ enabled, store this value to it to do so. */
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#define V850E_UART_CONFIG_INIT V850E_UARTB_CTL0_PWR
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/* Store this config value to disable the uart channel completely. */
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#define V850E_UART_CONFIG_FINI 0
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/* Setting/clearing these bits enable/disable TX/RX, respectively (but
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otherwise generally leave things running). */
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#define V850E_UART_CONFIG_RX_ENABLE V850E_UARTB_CTL0_RXE
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#define V850E_UART_CONFIG_TX_ENABLE V850E_UARTB_CTL0_TXE
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/* These masks define which config bits affect TX/RX modes, respectively. */
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#define V850E_UART_CONFIG_RX_BITS \
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(V850E_UARTB_CTL0_PS_MASK | V850E_UARTB_CTL0_CL_8)
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#define V850E_UART_CONFIG_TX_BITS \
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(V850E_UARTB_CTL0_PS_MASK | V850E_UARTB_CTL0_CL_8 | V850E_UARTB_CTL0_SL_2)
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static inline v850e_uart_config_t v850e_uart_calc_config (unsigned cflags)
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{
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v850e_uart_config_t config = 0;
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/* Figure out new configuration of control register. */
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if (cflags & CSTOPB)
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/* Number of stop bits, 1 or 2. */
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config |= V850E_UARTB_CTL0_SL_2;
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if ((cflags & CSIZE) == CS8)
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/* Number of data bits, 7 or 8. */
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config |= V850E_UARTB_CTL0_CL_8;
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if (! (cflags & PARENB))
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/* No parity check/generation. */
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config |= V850E_UARTB_CTL0_PS_NONE;
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else if (cflags & PARODD)
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/* Odd parity check/generation. */
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config |= V850E_UARTB_CTL0_PS_ODD;
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else
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/* Even parity check/generation. */
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config |= V850E_UARTB_CTL0_PS_EVEN;
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if (cflags & CREAD)
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/* Reading enabled. */
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config |= V850E_UARTB_CTL0_RXE;
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config |= V850E_UARTB_CTL0_PWR;
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config |= V850E_UARTB_CTL0_TXE; /* Writing is always enabled. */
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config |= V850E_UARTB_CTL0_DIR; /* LSB first. */
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return config;
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}
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/* This should delay as long as necessary for a recently written config
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setting to settle, before we turn the uart back on. */
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static inline void
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v850e_uart_config_delay (v850e_uart_config_t config, v850e_uart_speed_t speed)
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{
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/* The UART may not be reset properly unless we wait at least 2
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`basic-clocks' until turning on the TXE/RXE bits again.
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A `basic clock' is the clock used by the baud-rate generator,
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i.e., the cpu clock divided by the 2^new_clk_divlog2.
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The loop takes 2 insns, so loop CYCLES / 2 times. */
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register unsigned count = 1 << speed;
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while (--count != 0)
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/* nothing */;
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}
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/* RX/TX interface. */
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/* Return true if all characters awaiting transmission on uart channel N
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have been transmitted. */
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#define v850e_uart_xmit_done(n) \
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(! (V850E_UARTB_STR(n) & V850E_UARTB_STR_TSF))
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/* Wait for this to be true. */
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#define v850e_uart_wait_for_xmit_done(n) \
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do { } while (! v850e_uart_xmit_done (n))
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/* Return true if uart channel N is ready to transmit a character. */
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#define v850e_uart_xmit_ok(n) \
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(v850e_uart_xmit_done(n) && v850e_uart_cts(n))
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/* Wait for this to be true. */
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#define v850e_uart_wait_for_xmit_ok(n) \
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do { } while (! v850e_uart_xmit_ok (n))
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/* Write character CH to uart channel CHAN. */
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#define v850e_uart_putc(chan, ch) (V850E_UARTB_TX(chan) = (ch))
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/* Return latest character read on channel CHAN. */
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#define v850e_uart_getc(chan) V850E_UARTB_RX (chan)
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/* Return bit-mask of uart error status. */
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#define v850e_uart_err(chan) V850E_UARTB_STR (chan)
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/* Various error bits set in the error result. */
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#define V850E_UART_ERR_OVERRUN V850E_UARTB_STR_OVE
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#define V850E_UART_ERR_FRAME V850E_UARTB_STR_FE
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#define V850E_UART_ERR_PARITY V850E_UARTB_STR_PE
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#endif /* __V850_V850E_UARTB_H__ */
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