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b42d9023a3
In commit31cdd0c39c("powerpc/xmon: Fix SPR read/write commands and add command to dump SPRs") I added two uses of the "ld" instruction in spr_access.S. "ld" is a 64-bit instruction, so shouldn't be used on 32-bit CPUs. Replace it with PPC_LL which is a macro that gives us either "ld" or "lwz" depending on whether we're 64 or 32-bit. Fixes:31cdd0c39c("powerpc/xmon: Fix SPR read/write commands and add command to dump SPRs") Cc: stable@vger.kernel.org # v4.7+ Reported-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
46 lines
747 B
ArmAsm
46 lines
747 B
ArmAsm
#include <asm/ppc_asm.h>
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/* unsigned long xmon_mfspr(sprn, default_value) */
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_GLOBAL(xmon_mfspr)
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PPC_LL r5, .Lmfspr_table@got(r2)
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b xmon_mxspr
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/* void xmon_mtspr(sprn, new_value) */
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_GLOBAL(xmon_mtspr)
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PPC_LL r5, .Lmtspr_table@got(r2)
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b xmon_mxspr
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/*
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* r3 = sprn
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* r4 = default or new value
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* r5 = table base
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*/
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xmon_mxspr:
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/*
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* To index into the table of mxsprs we need:
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* i = (sprn & 0x3ff) * 8
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* or using rwlinm:
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* i = (sprn << 3) & (0x3ff << 3)
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*/
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rlwinm r3, r3, 3, 0x3ff << 3
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add r5, r5, r3
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mtctr r5
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mr r3, r4 /* put default_value in r3 for mfspr */
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bctr
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.Lmfspr_table:
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spr = 0
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.rept 1024
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mfspr r3, spr
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blr
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spr = spr + 1
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.endr
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.Lmtspr_table:
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spr = 0
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.rept 1024
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mtspr spr, r4
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blr
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spr = spr + 1
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.endr
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