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59b0113140
Add a pll mapping table for 19.2M in and 4.096M out. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
209 lines
4.3 KiB
C
209 lines
4.3 KiB
C
/*
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* rl6231.c - RL6231 class device shared support
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*
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* Copyright 2014 Realtek Semiconductor Corp.
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*
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* Author: Oder Chiou <oder_chiou@realtek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include "rl6231.h"
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/**
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* rl6231_get_pre_div - Return the value of pre divider.
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*
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* @map: map for setting.
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* @reg: register.
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* @sft: shift.
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*
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* Return the value of pre divider from given register value.
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* Return negative error code for unexpected register value.
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*/
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int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
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{
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int pd, val;
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regmap_read(map, reg, &val);
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val = (val >> sft) & 0x7;
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switch (val) {
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case 0:
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case 1:
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case 2:
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case 3:
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pd = val + 1;
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break;
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case 4:
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pd = 6;
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break;
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case 5:
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pd = 8;
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break;
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case 6:
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pd = 12;
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break;
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case 7:
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pd = 16;
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break;
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default:
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pd = -EINVAL;
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break;
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}
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return pd;
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}
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EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
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/**
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* rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
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*
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* @rate: base clock rate.
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*
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* Choose divider parameter that gives the highest possible DMIC frequency in
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* 1MHz - 3MHz range.
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*/
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int rl6231_calc_dmic_clk(int rate)
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{
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int div[] = {2, 3, 4, 6, 8, 12};
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int i;
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if (rate < 1000000 * div[0]) {
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pr_warn("Base clock rate %d is too low\n", rate);
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(div); i++) {
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if ((div[i] % 3) == 0)
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continue;
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/* find divider that gives DMIC frequency below 3.072MHz */
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if (3072000 * div[i] >= rate)
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return i;
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}
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pr_warn("Base clock rate %d is too high\n", rate);
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
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struct pll_calc_map {
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unsigned int pll_in;
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unsigned int pll_out;
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int k;
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int n;
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int m;
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bool m_bp;
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};
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static const struct pll_calc_map pll_preset_table[] = {
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{19200000, 4096000, 23, 14, 1, false},
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{19200000, 24576000, 3, 30, 3, false},
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};
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/**
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* rl6231_pll_calc - Calcualte PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K and bypass flag.
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*
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* Calcualte M/N/K code to configure PLL for codec.
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*
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* Returns 0 for success or negative error code.
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*/
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int rl6231_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rl6231_pll_code *pll_code)
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{
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int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
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int i, k, red, n_t, pll_out, in_t, out_t;
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int n = 0, m = 0, m_t = 0;
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int red_t = abs(freq_out - freq_in);
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bool bypass = false;
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if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
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if (freq_in == pll_preset_table[i].pll_in &&
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freq_out == pll_preset_table[i].pll_out) {
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k = pll_preset_table[i].k;
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m = pll_preset_table[i].m;
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n = pll_preset_table[i].n;
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bypass = pll_preset_table[i].m_bp;
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pr_debug("Use preset PLL parameter table\n");
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goto code_find;
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}
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}
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k = 100000000 / freq_out - 2;
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if (k > RL6231_PLL_K_MAX)
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k = RL6231_PLL_K_MAX;
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = freq_in / (k + 2);
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pll_out = freq_out / (n_t + 2);
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if (in_t < 0)
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continue;
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if (in_t == pll_out) {
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bypass = true;
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n = n_t;
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goto code_find;
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}
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red = abs(in_t - pll_out);
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if (red < red_t) {
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bypass = true;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / (m_t + 2);
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red = abs(out_t - pll_out);
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if (red < red_t) {
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bypass = false;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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pll_code->m_bp = bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = k;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rl6231_pll_calc);
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int rl6231_get_clk_info(int sclk, int rate)
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{
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int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
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if (sclk <= 0 || rate <= 0)
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return -EINVAL;
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rate = rate << 8;
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for (i = 0; i < ARRAY_SIZE(pd); i++)
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if (sclk == rate * pd[i])
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return i;
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
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MODULE_DESCRIPTION("RL6231 class device shared support");
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MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
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MODULE_LICENSE("GPL v2");
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