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3a6ba7dc77
The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a frequency synthesizer, jitter attenuator, digitally controlled oscillator (DCO), or a digital phase lock loop (DPLL). Typically these devices are used as timing references and clock sources for PTP applications. This patch adds support for the device. Co-developed-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
105 lines
2.5 KiB
C
105 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
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* synchronization devices.
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*
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* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef PTP_IDTCLOCKMATRIX_H
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#define PTP_IDTCLOCKMATRIX_H
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#include <linux/ktime.h>
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#include "idt8a340_reg.h"
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#define FW_FILENAME "idtcm.bin"
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#define MAX_PHC_PLL 4
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#define PLL_MASK_ADDR (0xFFA5)
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#define DEFAULT_PLL_MASK (0x04)
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#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
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#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
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#define OUTPUT_MASK_PLL0_ADDR (0xFFB0)
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#define OUTPUT_MASK_PLL1_ADDR (0xFFB2)
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#define OUTPUT_MASK_PLL2_ADDR (0xFFB4)
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#define OUTPUT_MASK_PLL3_ADDR (0xFFB6)
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#define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
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#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
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#define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
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#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
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#define POST_SM_RESET_DELAY_MS (3000)
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#define PHASE_PULL_IN_THRESHOLD_NS (150000)
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#define TOD_WRITE_OVERHEAD_COUNT_MAX (5)
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#define TOD_BYTE_COUNT (11)
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/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
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enum pll_mode {
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PLL_MODE_MIN = 0,
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PLL_MODE_NORMAL = PLL_MODE_MIN,
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PLL_MODE_WRITE_PHASE = 1,
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PLL_MODE_WRITE_FREQUENCY = 2,
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PLL_MODE_GPIO_INC_DEC = 3,
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PLL_MODE_SYNTHESIS = 4,
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PLL_MODE_PHASE_MEASUREMENT = 5,
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PLL_MODE_MAX = PLL_MODE_PHASE_MEASUREMENT,
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};
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enum hw_tod_write_trig_sel {
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HW_TOD_WR_TRIG_SEL_MIN = 0,
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HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
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HW_TOD_WR_TRIG_SEL_RESERVED = 1,
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HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
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HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
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HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
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HW_TOD_WR_TRIG_SEL_GPIO = 5,
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HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
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WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
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};
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struct idtcm;
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struct idtcm_channel {
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struct ptp_clock_info caps;
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struct ptp_clock *ptp_clock;
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struct idtcm *idtcm;
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u16 dpll_phase;
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u16 dpll_freq;
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u16 dpll_n;
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u16 dpll_ctrl_n;
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u16 dpll_phase_pull_in;
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u16 tod_read_primary;
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u16 tod_write;
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u16 tod_n;
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u16 hw_dpll_n;
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enum pll_mode pll_mode;
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u16 output_mask;
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};
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struct idtcm {
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struct idtcm_channel channel[MAX_PHC_PLL];
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struct i2c_client *client;
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u8 page_offset;
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u8 pll_mask;
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/* Overhead calculation for adjtime */
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u8 calculate_overhead_flag;
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s64 tod_write_overhead_ns;
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ktime_t start_time;
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/* Protects I2C read/modify/write registers from concurrent access */
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struct mutex reg_lock;
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};
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struct idtcm_fwrc {
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u8 hiaddr;
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u8 loaddr;
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u8 value;
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u8 reserved;
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} __packed;
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#endif /* PTP_IDTCLOCKMATRIX_H */
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