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a1dca315ce
If the controller has no PCIe module attached, accessing of the device configuration space causes a data bus error. Avoid this by checking the status of the PCIe link in advance, and indicate an error if the link is down. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4293/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
315 lines
7.0 KiB
C
315 lines
7.0 KiB
C
/*
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* Atheros AR724X PCI host controller driver
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/pci.h>
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x08000000
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#define AR724X_PCI_REG_RESET 0x18
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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#define AR724X_PCI_RESET_LINK_UP BIT(0)
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#define AR724X_PCI_INT_DEV0 BIT(14)
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#define AR724X_PCI_IRQ_COUNT 1
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#define AR7240_BAR0_WAR_VALUE 0xffff
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void __iomem *ar724x_pci_devcfg_base;
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static void __iomem *ar724x_pci_ctrl_base;
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static u32 ar724x_pci_bar0_value;
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static bool ar724x_pci_bar0_is_cached;
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static bool ar724x_pci_link_up;
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static inline bool ar724x_pci_check_link(void)
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{
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u32 reset;
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reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
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return reset & AR724X_PCI_RESET_LINK_UP;
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}
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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unsigned long flags;
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void __iomem *base;
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u32 data;
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if (!ar724x_pci_link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xff;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xffff;
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break;
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case 4:
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
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ar724x_pci_bar0_is_cached) {
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/* use the cached value */
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*value = ar724x_pci_bar0_value;
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} else {
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*value = data;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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unsigned long flags;
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void __iomem *base;
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u32 data;
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int s;
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if (!ar724x_pci_link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
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if (value != 0xffffffff) {
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/*
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* WAR for a hw issue. If the BAR0 register of the
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* device is set to the proper base address, the
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* memory space of the device is not accessible.
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*
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* Cache the intended value so it can be read back,
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* and write a SoC specific constant value to the
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* BAR0 register in order to make the device memory
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* accessible.
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*/
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ar724x_pci_bar0_is_cached = true;
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ar724x_pci_bar0_value = value;
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value = AR7240_BAR0_WAR_VALUE;
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} else {
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ar724x_pci_bar0_is_cached = false;
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}
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}
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) * 8);
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data &= ~(0xff << s);
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data |= ((value & 0xff) << s);
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break;
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case 2:
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s = ((where & 2) * 8);
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data &= ~(0xffff << s);
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data |= ((value & 0xffff) << s);
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break;
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case 4:
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data = value;
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ar724x_pci_ops = {
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.read = ar724x_pci_read,
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.write = ar724x_pci_write,
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};
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static struct resource ar724x_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ar724x_mem_resource = {
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.name = "PCI memory space",
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.start = AR724X_PCI_MEM_BASE,
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.end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller ar724x_pci_controller = {
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.pci_ops = &ar724x_pci_ops,
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.io_resource = &ar724x_io_resource,
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.mem_resource = &ar724x_mem_resource,
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};
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static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base;
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u32 pending;
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base = ar724x_pci_ctrl_base;
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pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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generic_handle_irq(ATH79_PCI_IRQ(0));
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else
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spurious_interrupt();
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}
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static void ar724x_pci_irq_unmask(struct irq_data *d)
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{
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void __iomem *base;
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u32 t;
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base = ar724x_pci_ctrl_base;
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switch (d->irq) {
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case ATH79_PCI_IRQ(0):
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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}
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}
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static void ar724x_pci_irq_mask(struct irq_data *d)
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{
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void __iomem *base;
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u32 t;
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base = ar724x_pci_ctrl_base;
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switch (d->irq) {
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case ATH79_PCI_IRQ(0):
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t & ~AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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}
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}
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static struct irq_chip ar724x_pci_irq_chip = {
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.name = "AR724X PCI ",
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.irq_mask = ar724x_pci_irq_mask,
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.irq_unmask = ar724x_pci_irq_unmask,
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.irq_mask_ack = ar724x_pci_irq_mask,
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};
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static void __init ar724x_pci_irq_init(int irq)
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{
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void __iomem *base;
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int i;
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base = ar724x_pci_ctrl_base;
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__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
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for (i = ATH79_PCI_IRQ_BASE;
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i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(irq, ar724x_pci_irq_handler);
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}
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int __init ar724x_pcibios_init(int irq)
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{
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int ret;
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ret = -ENOMEM;
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ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
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AR724X_PCI_CFG_SIZE);
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if (ar724x_pci_devcfg_base == NULL)
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goto err;
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ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
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AR724X_PCI_CTRL_SIZE);
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if (ar724x_pci_ctrl_base == NULL)
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goto err_unmap_devcfg;
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ar724x_pci_link_up = ar724x_pci_check_link();
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if (!ar724x_pci_link_up)
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pr_warn("ar724x: PCIe link is down\n");
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ar724x_pci_irq_init(irq);
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register_pci_controller(&ar724x_pci_controller);
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return PCIBIOS_SUCCESSFUL;
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err_unmap_devcfg:
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iounmap(ar724x_pci_devcfg_base);
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err:
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return ret;
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}
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