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The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
20 lines
571 B
Plaintext
20 lines
571 B
Plaintext
* Core Divider Clock bindings for Marvell MVEBU SoCs
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = nand (NAND clock)
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Required properties:
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- compatible : must be "marvell,armada-370-corediv-clock"
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- reg : must be the register address of Core Divider control register
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- #clock-cells : from common clock binding; shall be set to 1
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- clocks : must be set to the parent's phandle
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Example:
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corediv_clk: corediv-clocks@18740 {
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compatible = "marvell,armada-370-corediv-clock";
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reg = <0x18740 0xc>;
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#clock-cells = <1>;
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clocks = <&pll>;
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};
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