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07999587b7
Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
27 lines
762 B
Plaintext
27 lines
762 B
Plaintext
Tegra SoC PWFM controller
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Required properties:
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- compatible: should be one of:
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- "nvidia,tegra20-pwm"
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- "nvidia,tegra30-pwm"
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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the cells format.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- pwm
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Example:
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car 17>;
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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};
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