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cc604ddd11
Previously a check was done on an ID register at the base of a CPU's internal USB registers to determine if system interface regsiters were present. The check looked for an ID register that had the format ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to determine if a MPC5121 or MPC83xx/85xx was being used. There are two issues with this method: - The ID register is not defined on the MPC83xx/85xx CPUs, so its unclear what is being checked on them. - Newer CPUs such as the P4080 also don't document the ID register, but do share the same format as the MPC5121. Thus the previous code did not set 'have_sysif_regs' properly which results in the P4080 not properly initializing its USB ports. Using the device tree 'compatible' node is a cleaner way to determine if 'have_sysif_regs' should be set and resolves the USB initialization issue seen on the P4080. Tested on a P4080-based system and compile tested on mpc512x_defconfig with Freescale EHCI driver enabled. Cc: Anatolij Gustschin <agust@denx.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
46 lines
1.7 KiB
C
46 lines
1.7 KiB
C
/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
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* Copyright (c) 2005 MontaVista Software
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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#define PORT_PTS_UTMI (0<<30)
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#define PORT_PTS_ULPI (2<<30)
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#define PORT_PTS_SERIAL (3<<30)
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#define PORT_PTS_PTW (1<<28)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBGENCTRL 0x200
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#define USBGENCTRL_PPP (1 << 3)
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#define USBGENCTRL_PFP (1 << 2)
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#define FSL_SOC_USB_ISIPHYCTRL 0x204
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#define ISIPHYCTRL_PXE (1)
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#define ISIPHYCTRL_PHYE (1 << 4)
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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#endif /* _EHCI_FSL_H */
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