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94c12cc7d1
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
127 lines
2.6 KiB
C
127 lines
2.6 KiB
C
/*
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* include/asm-s390/sigp.h
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*
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* S390 version
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* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
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* Martin Schwidefsky (schwidefsky@de.ibm.com)
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* Heiko Carstens (heiko.carstens@de.ibm.com)
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*
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* sigp.h by D.J. Barrow (c) IBM 1999
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* contains routines / structures for signalling other S/390 processors in an
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* SMP configuration.
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*/
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#ifndef __SIGP__
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#define __SIGP__
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#include <asm/ptrace.h>
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#include <asm/atomic.h>
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/* get real cpu address from logical cpu number */
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extern volatile int __cpu_logical_map[];
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typedef enum
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{
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sigp_unassigned=0x0,
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sigp_sense,
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sigp_external_call,
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sigp_emergency_signal,
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sigp_start,
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sigp_stop,
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sigp_restart,
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sigp_unassigned1,
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sigp_unassigned2,
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sigp_stop_and_store_status,
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sigp_unassigned3,
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sigp_initial_cpu_reset,
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sigp_cpu_reset,
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sigp_set_prefix,
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sigp_store_status_at_address,
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sigp_store_extended_status_at_address
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} sigp_order_code;
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typedef __u32 sigp_status_word;
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typedef enum
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{
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sigp_order_code_accepted=0,
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sigp_status_stored,
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sigp_busy,
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sigp_not_operational
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} sigp_ccode;
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/*
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* Definitions for the external call
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*/
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/* 'Bit' signals, asynchronous */
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typedef enum
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{
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ec_schedule=0,
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ec_call_function,
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ec_bit_last
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} ec_bit_sig;
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/*
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* Signal processor
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*/
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static inline sigp_ccode
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signal_processor(__u16 cpu_addr, sigp_order_code order_code)
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{
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register unsigned long reg1 asm ("1") = 0;
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sigp_ccode ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode)
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: "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
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"a" (order_code) : "cc" , "memory");
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return ccode;
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}
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/*
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* Signal processor with parameter
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*/
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static inline sigp_ccode
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signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
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{
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register unsigned int reg1 asm ("1") = parameter;
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sigp_ccode ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode)
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: "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
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"a" (order_code) : "cc" , "memory");
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return ccode;
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}
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/*
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* Signal processor with parameter and return status
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*/
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static inline sigp_ccode
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signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
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sigp_order_code order_code)
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{
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register unsigned int reg1 asm ("1") = parameter;
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sigp_ccode ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode), "+d" (reg1)
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: "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
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: "cc" , "memory");
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*statusptr = reg1;
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return ccode;
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}
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#endif /* __SIGP__ */
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