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f713c6bf32
The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
140 lines
4.2 KiB
C
140 lines
4.2 KiB
C
/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/bcm-nsp.h>
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#include "clk-iproc.h"
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#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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.p_reset_shift = prs }
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#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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static void __init nsp_armpll_init(struct device_node *node)
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{
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iproc_armpll_setup(node);
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}
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CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
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static const struct iproc_pll_ctrl genpll = {
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.flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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.aon = AON_VAL(0x0, 1, 12, 0),
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.reset = RESET_VAL(0x0, 11, 10),
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.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
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.ndiv_int = REG_VAL(0x14, 20, 10),
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.ndiv_frac = REG_VAL(0x14, 0, 20),
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.pdiv = REG_VAL(0x18, 24, 3),
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.status = REG_VAL(0x20, 12, 1),
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};
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static const struct iproc_clk_ctrl genpll_clk[] = {
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[BCM_NSP_GENPLL_PHY_CLK] = {
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.channel = BCM_NSP_GENPLL_PHY_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 12, 6, 18),
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.mdiv = REG_VAL(0x18, 16, 8),
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},
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[BCM_NSP_GENPLL_ENET_SW_CLK] = {
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.channel = BCM_NSP_GENPLL_ENET_SW_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 13, 7, 19),
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.mdiv = REG_VAL(0x18, 8, 8),
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},
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[BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
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.channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 14, 8, 20),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_NSP_GENPLL_IPROCFAST_CLK] = {
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.channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 15, 9, 21),
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.mdiv = REG_VAL(0x1c, 16, 8),
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},
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[BCM_NSP_GENPLL_SATA1_CLK] = {
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.channel = BCM_NSP_GENPLL_SATA1_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 16, 10, 22),
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.mdiv = REG_VAL(0x1c, 8, 8),
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},
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[BCM_NSP_GENPLL_SATA2_CLK] = {
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.channel = BCM_NSP_GENPLL_SATA2_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 17, 11, 23),
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.mdiv = REG_VAL(0x1c, 0, 8),
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},
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};
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static void __init nsp_genpll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
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ARRAY_SIZE(genpll_clk));
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}
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CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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.aon = AON_VAL(0x0, 1, 24, 0),
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.reset = RESET_VAL(0x0, 23, 22),
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.dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4),
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.ndiv_int = REG_VAL(0x4, 20, 8),
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.ndiv_frac = REG_VAL(0x4, 0, 20),
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.pdiv = REG_VAL(0x4, 28, 3),
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.status = REG_VAL(0x10, 12, 1),
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};
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static const struct iproc_clk_ctrl lcpll0_clk[] = {
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[BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
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.channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 6, 3, 9),
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.mdiv = REG_VAL(0x8, 24, 8),
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},
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[BCM_NSP_LCPLL0_SDIO_CLK] = {
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.channel = BCM_NSP_LCPLL0_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 7, 4, 10),
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.mdiv = REG_VAL(0x8, 16, 8),
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},
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[BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
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.channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 8, 5, 11),
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.mdiv = REG_VAL(0x8, 8, 8),
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},
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};
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static void __init nsp_lcpll0_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
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ARRAY_SIZE(lcpll0_clk));
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}
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CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
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