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7d6ab9b862
Separate out common dts pieces from highbank dts and add support for Calxeda ECX-2000 (Midway) SOC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
238 lines
5.1 KiB
Plaintext
238 lines
5.1 KiB
Plaintext
/*
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/ {
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chosen {
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bootargs = "console=ttyAMA0";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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sata@ffe08000 {
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compatible = "calxeda,hb-ahci";
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reg = <0xffe08000 0x10000>;
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interrupts = <0 83 4>;
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dma-coherent;
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calxeda,port-phys = <&combophy5 0 &combophy0 0
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&combophy0 1 &combophy0 2
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&combophy0 3>;
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};
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sdhci@ffe0e000 {
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compatible = "calxeda,hb-sdhci";
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reg = <0xffe0e000 0x1000>;
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interrupts = <0 90 4>;
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clocks = <&eclk>;
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status = "disabled";
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};
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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ipc@fff20000 {
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compatible = "arm,pl320", "arm,primecell";
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reg = <0xfff20000 0x1000>;
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interrupts = <0 7 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpioe: gpio@fff30000 {
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#gpio-cells = <2>;
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compatible = "arm,pl061", "arm,primecell";
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gpio-controller;
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reg = <0xfff30000 0x1000>;
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interrupts = <0 14 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpiof: gpio@fff31000 {
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#gpio-cells = <2>;
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compatible = "arm,pl061", "arm,primecell";
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gpio-controller;
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reg = <0xfff31000 0x1000>;
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interrupts = <0 15 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpiog: gpio@fff32000 {
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#gpio-cells = <2>;
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compatible = "arm,pl061", "arm,primecell";
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gpio-controller;
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reg = <0xfff32000 0x1000>;
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interrupts = <0 16 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpioh: gpio@fff33000 {
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#gpio-cells = <2>;
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compatible = "arm,pl061", "arm,primecell";
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gpio-controller;
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reg = <0xfff33000 0x1000>;
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interrupts = <0 17 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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timer@fff34000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xfff34000 0x1000>;
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interrupts = <0 18 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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rtc@fff35000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0xfff35000 0x1000>;
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interrupts = <0 19 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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serial@fff36000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xfff36000 0x1000>;
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interrupts = <0 20 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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smic@fff3a000 {
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compatible = "ipmi-smic";
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device_type = "ipmi";
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reg = <0xfff3a000 0x1000>;
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interrupts = <0 24 4>;
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reg-size = <4>;
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reg-spacing = <4>;
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};
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sregs@fff3c000 {
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compatible = "calxeda,hb-sregs";
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reg = <0xfff3c000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333000>;
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};
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ddrpll: ddrpll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x108>;
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};
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a9pll: a9pll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x100>;
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};
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a9periphclk: a9periphclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-a9periph-clock";
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clocks = <&a9pll>;
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reg = <0x104>;
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};
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a9bclk: a9bclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-a9bus-clock";
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clocks = <&a9pll>;
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reg = <0x104>;
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};
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emmcpll: emmcpll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x10C>;
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};
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eclk: eclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-emmc-clock";
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clocks = <&emmcpll>;
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reg = <0x114>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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};
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};
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};
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dma@fff3d000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xfff3d000 0x1000>;
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interrupts = <0 92 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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ethernet@fff50000 {
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compatible = "calxeda,hb-xgmac";
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reg = <0xfff50000 0x1000>;
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interrupts = <0 77 4 0 78 4 0 79 4>;
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dma-coherent;
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};
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ethernet@fff51000 {
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compatible = "calxeda,hb-xgmac";
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reg = <0xfff51000 0x1000>;
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interrupts = <0 80 4 0 81 4 0 82 4>;
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dma-coherent;
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};
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combophy0: combo-phy@fff58000 {
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compatible = "calxeda,hb-combophy";
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#phy-cells = <1>;
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reg = <0xfff58000 0x1000>;
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phydev = <5>;
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};
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combophy5: combo-phy@fff5d000 {
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compatible = "calxeda,hb-combophy";
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#phy-cells = <1>;
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reg = <0xfff5d000 0x1000>;
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phydev = <31>;
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};
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};
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};
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