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https://github.com/edk2-porting/linux-next.git
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e578bbdeb8
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
182 lines
9.0 KiB
C
182 lines
9.0 KiB
C
/*
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* bfin_ppi.h - interface to Blackfin PPIs
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*
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* Copyright 2005-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __ASM_BFIN_PPI_H__
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#define __ASM_BFIN_PPI_H__
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#include <linux/types.h>
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#include <asm/blackfin.h>
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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/*
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* bfin ppi registers layout
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*/
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struct bfin_ppi_regs {
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__BFP(control);
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__BFP(status);
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__BFP(count);
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__BFP(delay);
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__BFP(frame);
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};
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/*
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* bfin eppi registers layout
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*/
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struct bfin_eppi_regs {
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__BFP(status);
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__BFP(hcount);
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__BFP(hdelay);
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__BFP(vcount);
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__BFP(vdelay);
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__BFP(frame);
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__BFP(line);
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__BFP(clkdiv);
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u32 control;
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u32 fs1w_hbl;
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u32 fs1p_avpl;
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u32 fs2w_lvb;
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u32 fs2p_lavf;
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u32 clip;
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};
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/*
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* bfin eppi3 registers layout
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*/
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struct bfin_eppi3_regs {
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u32 stat;
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u32 hcnt;
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u32 hdly;
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u32 vcnt;
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u32 vdly;
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u32 frame;
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u32 line;
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u32 clkdiv;
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u32 ctl;
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u32 fs1_wlhb;
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u32 fs1_paspl;
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u32 fs2_wlvb;
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u32 fs2_palpf;
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u32 imsk;
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u32 oddclip;
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u32 evenclip;
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u32 fs1_dly;
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u32 fs2_dly;
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u32 ctl2;
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};
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#undef __BFP
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#ifdef EPPI0_CTL2
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#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
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#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
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#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
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#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
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#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
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#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
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#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
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#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
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#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
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#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
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#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
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#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
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#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
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#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
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#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
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#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
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#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
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#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
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#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
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#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
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#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
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#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
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#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
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#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
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#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
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#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
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#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
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#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
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#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
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#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
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#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
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#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
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#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
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#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
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#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
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#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
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#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
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#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
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#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
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#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
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#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
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#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
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#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
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#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
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#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
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#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
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#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
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#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
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#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
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#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
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#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
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#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
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#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
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#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
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#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
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#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
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#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
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#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
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#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
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#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
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#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
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#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
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#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
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#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
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#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
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#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
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#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
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#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
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#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
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#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
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#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
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#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
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#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
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#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
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#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
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#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
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#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
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#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
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#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
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#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
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#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
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#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
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#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
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#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
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#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
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#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
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#endif
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#endif
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