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94dee171df
> #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
131 lines
2.8 KiB
C
131 lines
2.8 KiB
C
/*
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* linux/arch/mips/dec/kn02-irq.c
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*
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* DECstation 5000/200 (KN02) Control and Status Register
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* interrupts.
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*
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* Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/dec/kn02.h>
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/*
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* Bits 7:0 of the Control Register are write-only -- the
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* corresponding bits of the Status Register have a different
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* meaning. Hence we use a cache. It speeds up things a bit
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* as well.
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*
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* There is no default value -- it has to be initialized.
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*/
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u32 cached_kn02_csr;
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DEFINE_SPINLOCK(kn02_lock);
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static int kn02_irq_base;
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static inline void unmask_kn02_irq(unsigned int irq)
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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}
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static inline void mask_kn02_irq(unsigned int irq)
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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}
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static inline void enable_kn02_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&kn02_lock, flags);
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unmask_kn02_irq(irq);
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spin_unlock_irqrestore(&kn02_lock, flags);
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}
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static inline void disable_kn02_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&kn02_lock, flags);
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mask_kn02_irq(irq);
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spin_unlock_irqrestore(&kn02_lock, flags);
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}
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static unsigned int startup_kn02_irq(unsigned int irq)
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{
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enable_kn02_irq(irq);
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return 0;
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}
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#define shutdown_kn02_irq disable_kn02_irq
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static void ack_kn02_irq(unsigned int irq)
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{
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spin_lock(&kn02_lock);
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mask_kn02_irq(irq);
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spin_unlock(&kn02_lock);
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iob();
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}
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static void end_kn02_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_kn02_irq(irq);
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}
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static struct irq_chip kn02_irq_type = {
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.typename = "KN02-CSR",
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.startup = startup_kn02_irq,
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.shutdown = shutdown_kn02_irq,
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.enable = enable_kn02_irq,
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.disable = disable_kn02_irq,
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.ack = ack_kn02_irq,
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.end = end_kn02_irq,
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};
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void __init init_kn02_irqs(int base)
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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unsigned long flags;
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int i;
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/* Mask interrupts. */
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spin_lock_irqsave(&kn02_lock, flags);
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cached_kn02_csr &= ~KN02_CSR_IOINTEN;
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*csr = cached_kn02_csr;
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iob();
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spin_unlock_irqrestore(&kn02_lock, flags);
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for (i = base; i < base + KN02_IRQ_LINES; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &kn02_irq_type;
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}
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kn02_irq_base = base;
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}
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