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8ff120e530
This patch fixes a bug in the CORE dpll scaling sequence which was errouneously clearing some bits in the SDRC DLLA CTRL register and hence causing a freeze. The issue was observed only on platforms which scale CORE dpll to < 83Mhz and hence program the DLL in fixed delay mode. Issue reported by Limei Wang <E12499@motorola.com>, with debugging assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish Ghongdemath <girishsg@ti.com>. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: Limei Wang <E12499@motorola.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Girish Ghongdemath <girishsg@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: updated patch description to include collaboration credits] |
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