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2f508a955a
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Standard functionality for the common clock API.
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*/
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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/*
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* DOC: basic fixed multiplier and divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is fixed. clk->rate = parent->rate / div * mult
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
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static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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unsigned long long int rate;
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rate = (unsigned long long int)parent_rate * fix->mult;
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do_div(rate, fix->div);
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return (unsigned long)rate;
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}
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static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent;
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best_parent = (rate / fix->mult) * fix->div;
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*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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}
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return (*prate / fix->div) * fix->mult;
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}
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static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* We must report success but we can do so unconditionally because
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* clk_factor_round_rate returns values that ensure this call is a
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* nop.
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*/
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return 0;
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}
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const struct clk_ops clk_fixed_factor_ops = {
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.round_rate = clk_factor_round_rate,
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.set_rate = clk_factor_set_rate,
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.recalc_rate = clk_factor_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
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struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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struct clk_fixed_factor *fix;
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struct clk_init_data init;
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struct clk *clk;
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fix = kmalloc(sizeof(*fix), GFP_KERNEL);
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if (!fix)
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return ERR_PTR(-ENOMEM);
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/* struct clk_fixed_factor assignments */
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fix->mult = mult;
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fix->div = div;
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fix->hw.init = &init;
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(dev, &fix->hw);
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if (IS_ERR(clk))
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kfree(fix);
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return clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
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#ifdef CONFIG_OF
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/**
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* of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
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*/
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void __init of_fixed_factor_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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const char *clk_name = node->name;
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const char *parent_name;
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u32 div, mult;
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if (of_property_read_u32(node, "clock-div", &div)) {
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pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
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__func__, node->name);
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return;
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}
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if (of_property_read_u32(node, "clock-mult", &mult)) {
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pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n",
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__func__, node->name);
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return;
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}
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
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mult, div);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup);
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CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
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of_fixed_factor_clk_setup);
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#endif
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