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51c1327876
The SH Mobile LCD controller (LCDC) DRM driver supports the main graphics plane in RGB and YUV formats, as well as the overlay planes (in alpha-blending mode only). Only flat panel outputs using the parallel interface are supported. Support for SYS panels, HDMI and DSI is currently not implemented. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
312 lines
9.0 KiB
C
312 lines
9.0 KiB
C
/*
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* shmob_drm_regs.h -- SH Mobile DRM registers
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*
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* Copyright (C) 2012 Renesas Corporation
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*
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* Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __SHMOB_DRM_REGS_H__
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#define __SHMOB_DRM_REGS_H__
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#include <linux/io.h>
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/* Register definitions */
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#define LDDCKPAT1R 0x400
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#define LDDCKPAT2R 0x404
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#define LDDCKR 0x410
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#define LDDCKR_ICKSEL_BUS (0 << 16)
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#define LDDCKR_ICKSEL_MIPI (1 << 16)
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#define LDDCKR_ICKSEL_HDMI (2 << 16)
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#define LDDCKR_ICKSEL_EXT (3 << 16)
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#define LDDCKR_ICKSEL_MASK (7 << 16)
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#define LDDCKR_MOSEL (1 << 6)
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#define LDDCKSTPR 0x414
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#define LDDCKSTPR_DCKSTS (1 << 16)
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#define LDDCKSTPR_DCKSTP (1 << 0)
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#define LDMT1R 0x418
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#define LDMT1R_VPOL (1 << 28)
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#define LDMT1R_HPOL (1 << 27)
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#define LDMT1R_DWPOL (1 << 26)
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#define LDMT1R_DIPOL (1 << 25)
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#define LDMT1R_DAPOL (1 << 24)
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#define LDMT1R_HSCNT (1 << 17)
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#define LDMT1R_DWCNT (1 << 16)
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#define LDMT1R_IFM (1 << 12)
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#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
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#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
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#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
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#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
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#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
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#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
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#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
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#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
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#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
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#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
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#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
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#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
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#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
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#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
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#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
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#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
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#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
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#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
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#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
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#define LDMT1R_MIFTYP_MASK (0xf << 0)
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#define LDMT2R 0x41c
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#define LDMT2R_CSUP_MASK (7 << 26)
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#define LDMT2R_CSUP_SHIFT 26
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#define LDMT2R_RSV (1 << 25)
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#define LDMT2R_VSEL (1 << 24)
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#define LDMT2R_WCSC_MASK (0xff << 16)
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#define LDMT2R_WCSC_SHIFT 16
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#define LDMT2R_WCEC_MASK (0xff << 8)
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#define LDMT2R_WCEC_SHIFT 8
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#define LDMT2R_WCLW_MASK (0xff << 0)
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#define LDMT2R_WCLW_SHIFT 0
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#define LDMT3R 0x420
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#define LDMT3R_RDLC_MASK (0x3f << 24)
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#define LDMT3R_RDLC_SHIFT 24
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#define LDMT3R_RCSC_MASK (0xff << 16)
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#define LDMT3R_RCSC_SHIFT 16
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#define LDMT3R_RCEC_MASK (0xff << 8)
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#define LDMT3R_RCEC_SHIFT 8
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#define LDMT3R_RCLW_MASK (0xff << 0)
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#define LDMT3R_RCLW_SHIFT 0
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#define LDDFR 0x424
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#define LDDFR_CF1 (1 << 18)
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#define LDDFR_CF0 (1 << 17)
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#define LDDFR_CC (1 << 16)
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#define LDDFR_YF_420 (0 << 8)
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#define LDDFR_YF_422 (1 << 8)
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#define LDDFR_YF_444 (2 << 8)
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#define LDDFR_YF_MASK (3 << 8)
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#define LDDFR_PKF_ARGB32 (0x00 << 0)
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#define LDDFR_PKF_RGB16 (0x03 << 0)
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#define LDDFR_PKF_RGB24 (0x0b << 0)
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#define LDDFR_PKF_MASK (0x1f << 0)
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#define LDSM1R 0x428
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#define LDSM1R_OS (1 << 0)
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#define LDSM2R 0x42c
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#define LDSM2R_OSTRG (1 << 0)
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#define LDSA1R 0x430
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#define LDSA2R 0x434
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#define LDMLSR 0x438
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#define LDWBFR 0x43c
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#define LDWBCNTR 0x440
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#define LDWBAR 0x444
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#define LDHCNR 0x448
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#define LDHSYNR 0x44c
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#define LDVLNR 0x450
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#define LDVSYNR 0x454
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#define LDHPDR 0x458
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#define LDVPDR 0x45c
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#define LDPMR 0x460
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#define LDPMR_LPS (3 << 0)
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#define LDINTR 0x468
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#define LDINTR_FE (1 << 10)
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#define LDINTR_VSE (1 << 9)
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#define LDINTR_VEE (1 << 8)
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#define LDINTR_FS (1 << 2)
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#define LDINTR_VSS (1 << 1)
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#define LDINTR_VES (1 << 0)
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#define LDINTR_STATUS_MASK (0xff << 0)
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#define LDSR 0x46c
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#define LDSR_MSS (1 << 10)
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#define LDSR_MRS (1 << 8)
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#define LDSR_AS (1 << 1)
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#define LDCNT1R 0x470
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#define LDCNT1R_DE (1 << 0)
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#define LDCNT2R 0x474
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#define LDCNT2R_BR (1 << 8)
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#define LDCNT2R_MD (1 << 3)
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#define LDCNT2R_SE (1 << 2)
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#define LDCNT2R_ME (1 << 1)
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#define LDCNT2R_DO (1 << 0)
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#define LDRCNTR 0x478
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#define LDRCNTR_SRS (1 << 17)
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#define LDRCNTR_SRC (1 << 16)
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#define LDRCNTR_MRS (1 << 1)
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#define LDRCNTR_MRC (1 << 0)
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#define LDDDSR 0x47c
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#define LDDDSR_LS (1 << 2)
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#define LDDDSR_WS (1 << 1)
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#define LDDDSR_BS (1 << 0)
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#define LDHAJR 0x4a0
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#define LDDWD0R 0x800
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#define LDDWDxR_WDACT (1 << 28)
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#define LDDWDxR_RSW (1 << 24)
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#define LDDRDR 0x840
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#define LDDRDR_RSR (1 << 24)
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#define LDDRDR_DRD_MASK (0x3ffff << 0)
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#define LDDWAR 0x900
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#define LDDWAR_WA (1 << 0)
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#define LDDRAR 0x904
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#define LDDRAR_RA (1 << 0)
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#define LDBCR 0xb00
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#define LDBCR_UPC(n) (1 << ((n) + 16))
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#define LDBCR_UPF(n) (1 << ((n) + 8))
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#define LDBCR_UPD(n) (1 << ((n) + 0))
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#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
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#define LDBBSIFR_EN (1 << 31)
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#define LDBBSIFR_VS (1 << 29)
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#define LDBBSIFR_BRSEL (1 << 28)
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#define LDBBSIFR_MX (1 << 27)
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#define LDBBSIFR_MY (1 << 26)
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#define LDBBSIFR_CV3 (3 << 24)
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#define LDBBSIFR_CV2 (2 << 24)
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#define LDBBSIFR_CV1 (1 << 24)
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#define LDBBSIFR_CV0 (0 << 24)
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#define LDBBSIFR_CV_MASK (3 << 24)
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#define LDBBSIFR_LAY_MASK (0xff << 16)
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#define LDBBSIFR_LAY_SHIFT 16
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#define LDBBSIFR_ROP3_MASK (0xff << 16)
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#define LDBBSIFR_ROP3_SHIFT 16
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#define LDBBSIFR_AL_PL8 (3 << 14)
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#define LDBBSIFR_AL_PL1 (2 << 14)
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#define LDBBSIFR_AL_PK (1 << 14)
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#define LDBBSIFR_AL_1 (0 << 14)
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#define LDBBSIFR_AL_MASK (3 << 14)
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#define LDBBSIFR_SWPL (1 << 10)
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#define LDBBSIFR_SWPW (1 << 9)
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#define LDBBSIFR_SWPB (1 << 8)
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#define LDBBSIFR_RY (1 << 7)
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#define LDBBSIFR_CHRR_420 (2 << 0)
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#define LDBBSIFR_CHRR_422 (1 << 0)
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#define LDBBSIFR_CHRR_444 (0 << 0)
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#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
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#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
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#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
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#define LDBBSIFR_RPKF_MASK (0x1f << 0)
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#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
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#define LDBBSSZR_BVSS_MASK (0xfff << 16)
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#define LDBBSSZR_BVSS_SHIFT 16
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#define LDBBSSZR_BHSS_MASK (0xfff << 0)
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#define LDBBSSZR_BHSS_SHIFT 0
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#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
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#define LDBBLOCR_CVLC_MASK (0xfff << 16)
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#define LDBBLOCR_CVLC_SHIFT 16
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#define LDBBLOCR_CHLC_MASK (0xfff << 0)
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#define LDBBLOCR_CHLC_SHIFT 0
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#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
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#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
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#define LDBBSMWR_BSMWA_SHIFT 16
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#define LDBBSMWR_BSMW_MASK (0xffff << 0)
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#define LDBBSMWR_BSMW_SHIFT 0
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#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
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#define LDBBSAYR_FG1A_MASK (0xff << 24)
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#define LDBBSAYR_FG1A_SHIFT 24
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#define LDBBSAYR_FG1R_MASK (0xff << 16)
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#define LDBBSAYR_FG1R_SHIFT 16
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#define LDBBSAYR_FG1G_MASK (0xff << 8)
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#define LDBBSAYR_FG1G_SHIFT 8
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#define LDBBSAYR_FG1B_MASK (0xff << 0)
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#define LDBBSAYR_FG1B_SHIFT 0
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#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
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#define LDBBSACR_FG2A_MASK (0xff << 24)
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#define LDBBSACR_FG2A_SHIFT 24
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#define LDBBSACR_FG2R_MASK (0xff << 16)
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#define LDBBSACR_FG2R_SHIFT 16
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#define LDBBSACR_FG2G_MASK (0xff << 8)
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#define LDBBSACR_FG2G_SHIFT 8
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#define LDBBSACR_FG2B_MASK (0xff << 0)
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#define LDBBSACR_FG2B_SHIFT 0
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#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
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#define LDBBSAAR_AP_MASK (0xff << 24)
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#define LDBBSAAR_AP_SHIFT 24
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#define LDBBSAAR_R_MASK (0xff << 16)
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#define LDBBSAAR_R_SHIFT 16
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#define LDBBSAAR_GY_MASK (0xff << 8)
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#define LDBBSAAR_GY_SHIFT 8
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#define LDBBSAAR_B_MASK (0xff << 0)
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#define LDBBSAAR_B_SHIFT 0
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#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
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#define LDBBPPCR_AP_MASK (0xff << 24)
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#define LDBBPPCR_AP_SHIFT 24
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#define LDBBPPCR_R_MASK (0xff << 16)
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#define LDBBPPCR_R_SHIFT 16
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#define LDBBPPCR_GY_MASK (0xff << 8)
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#define LDBBPPCR_GY_SHIFT 8
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#define LDBBPPCR_B_MASK (0xff << 0)
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#define LDBBPPCR_B_SHIFT 0
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#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
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#define LDBBBGCL_BGA_MASK (0xff << 24)
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#define LDBBBGCL_BGA_SHIFT 24
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#define LDBBBGCL_BGR_MASK (0xff << 16)
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#define LDBBBGCL_BGR_SHIFT 16
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#define LDBBBGCL_BGG_MASK (0xff << 8)
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#define LDBBBGCL_BGG_SHIFT 8
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#define LDBBBGCL_BGB_MASK (0xff << 0)
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#define LDBBBGCL_BGB_SHIFT 0
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#define LCDC_SIDE_B_OFFSET 0x1000
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#define LCDC_MIRROR_OFFSET 0x2000
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static inline bool lcdc_is_banked(u32 reg)
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{
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switch (reg) {
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case LDMT1R:
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case LDMT2R:
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case LDMT3R:
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case LDDFR:
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case LDSM1R:
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case LDSA1R:
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case LDSA2R:
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case LDMLSR:
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case LDWBFR:
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case LDWBCNTR:
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case LDWBAR:
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case LDHCNR:
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case LDHSYNR:
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case LDVLNR:
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case LDVSYNR:
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case LDHPDR:
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case LDVPDR:
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case LDHAJR:
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return true;
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default:
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return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3);
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}
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}
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static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg,
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u32 data)
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{
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iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET);
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}
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static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data)
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{
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iowrite32(data, sdev->mmio + reg);
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if (lcdc_is_banked(reg))
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iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET);
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}
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static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg)
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{
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return ioread32(sdev->mmio + reg);
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}
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static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg,
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u32 mask, u32 until)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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while ((lcdc_read(sdev, reg) & mask) != until) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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#endif /* __SHMOB_DRM_REGS_H__ */
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