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306 lines
5.2 KiB
Plaintext
306 lines
5.2 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/config-language.txt.
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#
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mainmenu "Linux/SH64 Kernel Configuration"
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config SUPERH
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bool
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default y
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config SUPERH64
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bool
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default y
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config MMU
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bool
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default y
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config QUICKLIST
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def_bool y
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config RWSEM_GENERIC_SPINLOCK
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bool
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default y
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config GENERIC_FIND_NEXT_BIT
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bool
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default y
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config GENERIC_HWEIGHT
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bool
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default y
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config GENERIC_CALIBRATE_DELAY
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bool
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default y
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config RWSEM_XCHGADD_ALGORITHM
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bool
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config ARCH_HAS_ILOG2_U32
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bool
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default n
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config ARCH_HAS_ILOG2_U64
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bool
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default n
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source init/Kconfig
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menu "System type"
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choice
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prompt "SuperH system type"
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default SH_SIMULATOR
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config SH_GENERIC
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bool "Generic"
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config SH_SIMULATOR
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bool "Simulator"
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config SH_CAYMAN
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bool "Cayman"
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config SH_ROMRAM
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bool "ROM/RAM"
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config SH_HARP
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bool "ST50-Harp"
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endchoice
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choice
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prompt "Processor family"
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default CPU_SH5
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config CPU_SH5
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bool "SH-5"
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endchoice
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choice
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prompt "Processor type"
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config CPU_SUBTYPE_SH5_101
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bool "SH5-101"
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depends on CPU_SH5
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config CPU_SUBTYPE_SH5_103
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bool "SH5-103"
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depends on CPU_SH5
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endchoice
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choice
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prompt "Endianness"
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default LITTLE_ENDIAN
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config LITTLE_ENDIAN
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bool "Little-Endian"
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config BIG_ENDIAN
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bool "Big-Endian"
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endchoice
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config SH_FPU
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bool "FPU support"
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default y
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config SH64_FPU_DENORM_FLUSH
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depends on SH_FPU
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bool "Flush floating point denorms to zero"
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choice
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prompt "Page table levels"
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default SH64_PGTABLE_2_LEVEL
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config SH64_PGTABLE_2_LEVEL
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bool "2"
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config SH64_PGTABLE_3_LEVEL
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bool "3"
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endchoice
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choice
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prompt "HugeTLB page size"
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depends on HUGETLB_PAGE && MMU
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default HUGETLB_PAGE_SIZE_64K
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config HUGETLB_PAGE_SIZE_64K
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bool "64K"
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config HUGETLB_PAGE_SIZE_1MB
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bool "1MB"
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config HUGETLB_PAGE_SIZE_512MB
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bool "512MB"
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endchoice
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config SH64_USER_MISALIGNED_FIXUP
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bool "Fixup misaligned loads/stores occurring in user mode"
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comment "Memory options"
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config CACHED_MEMORY_OFFSET
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hex "Cached Area Offset"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "20000000"
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config MEMORY_START
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hex "Physical memory start address"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "80000000"
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config MEMORY_SIZE_IN_MB
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int "Memory size (in MB)" if SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "64" if SH_HARP || SH_CAYMAN
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default "8" if SH_SIMULATOR
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comment "Cache options"
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config DCACHE_DISABLED
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bool "DCache Disabling"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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choice
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prompt "DCache mode"
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depends on !DCACHE_DISABLED && !SH_SIMULATOR
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default DCACHE_WRITE_BACK
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config DCACHE_WRITE_BACK
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bool "Write-back"
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config DCACHE_WRITE_THROUGH
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bool "Write-through"
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endchoice
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config ICACHE_DISABLED
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bool "ICache Disabling"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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config PCIDEVICE_MEMORY_START
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hex
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "C0000000"
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config DEVICE_MEMORY_START
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hex
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "E0000000"
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config FLASH_MEMORY_START
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hex "Flash memory/on-chip devices start address"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "00000000"
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config PCI_BLOCK_START
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hex "PCI block start address"
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depends on SH_HARP || SH_CAYMAN || SH_SIMULATOR
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default "40000000"
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comment "CPU Subtype specific options"
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config SH64_ID2815_WORKAROUND
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bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
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comment "Misc options"
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config HEARTBEAT
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bool "Heartbeat LED"
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config HDSP253_LED
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bool "Support for HDSP-253 LED"
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depends on SH_CAYMAN
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config SH_DMA
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tristate "DMA controller (DMAC) support"
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config PREEMPT
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bool "Preemptible Kernel (EXPERIMENTAL)"
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depends on EXPERIMENTAL
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source "mm/Kconfig"
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endmenu
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menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
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config ISA
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bool
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config SBUS
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bool
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config PCI
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bool "PCI support"
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help
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Find out whether you have a PCI motherboard. PCI is the name of a
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bus system, i.e. the way the CPU talks to the other stuff inside
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your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
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VESA. If you have PCI, say Y, otherwise N.
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The PCI-HOWTO, available from
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<http://www.tldp.org/docs.html#howto>, contains valuable
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information about which PCI hardware does work under Linux and which
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doesn't.
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config SH_PCIDMA_NONCOHERENT
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bool "Cache and PCI noncoherent"
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depends on PCI
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default y
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help
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Enable this option if your platform does not have a CPU cache which
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remains coherent with PCI DMA. It is safest to say 'Y', although you
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will see better performance if you can say 'N', because the PCI DMA
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code will not have to flush the CPU's caches. If you have a PCI host
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bridge integrated with your SH CPU, refer carefully to the chip specs
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to see if you can say 'N' here. Otherwise, leave it as 'Y'.
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source "drivers/pci/Kconfig"
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source "drivers/pcmcia/Kconfig"
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source "drivers/pci/hotplug/Kconfig"
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endmenu
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menu "Executable file formats"
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source "fs/Kconfig.binfmt"
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endmenu
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source "net/Kconfig"
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source "drivers/Kconfig"
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source "fs/Kconfig"
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source "arch/sh64/oprofile/Kconfig"
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source "arch/sh64/Kconfig.debug"
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source "security/Kconfig"
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source "crypto/Kconfig"
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source "lib/Kconfig"
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#
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# Use the generic interrupt handling code in kernel/irq/:
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#
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config GENERIC_HARDIRQS
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bool
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default y
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config GENERIC_IRQ_PROBE
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bool
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default y
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