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cb0f253803
Implement an ARM delay timer to be used for udelay() on Armada 37x platforms. This allows us to skip the delay loop calibration at boot, saving 180ms on the boot time of the kernel (which is around 10%). It also means that udelay() will be unaffected by CPU frequency changes when cpufreq is enabled on these platforms. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
387 lines
9.8 KiB
C
387 lines
9.8 KiB
C
/*
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* Marvell Armada 370/XP SoC timer handling.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Timer 0 is used as free-running clocksource, while timer 1 is
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* used as clock_event_device.
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*
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* ---
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* Clocksource driver for Armada 370 and Armada XP SoC.
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* This driver implements one compatible string for each SoC, given
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* each has its own characteristics:
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*
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* * Armada 370 has no 25 MHz fixed timer.
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*
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* * Armada XP cannot work properly without such 25 MHz fixed timer as
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* doing otherwise leads to using a clocksource whose frequency varies
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* when doing cpufreq frequency changes.
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*
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* See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/timer.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/sched_clock.h>
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#include <linux/percpu.h>
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#include <linux/syscore_ops.h>
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#include <asm/delay.h>
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/*
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* Timer block registers.
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*/
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#define TIMER_CTRL_OFF 0x0000
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#define TIMER0_EN BIT(0)
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#define TIMER0_RELOAD_EN BIT(1)
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#define TIMER0_25MHZ BIT(11)
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#define TIMER0_DIV(div) ((div) << 19)
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#define TIMER1_EN BIT(2)
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#define TIMER1_RELOAD_EN BIT(3)
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#define TIMER1_25MHZ BIT(12)
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#define TIMER1_DIV(div) ((div) << 22)
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#define TIMER_EVENTS_STATUS 0x0004
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#define TIMER0_CLR_MASK (~0x1)
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#define TIMER1_CLR_MASK (~0x100)
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#define TIMER0_RELOAD_OFF 0x0010
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#define TIMER0_VAL_OFF 0x0014
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#define TIMER1_RELOAD_OFF 0x0018
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#define TIMER1_VAL_OFF 0x001c
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#define LCL_TIMER_EVENTS_STATUS 0x0028
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/* Global timers are connected to the coherency fabric clock, and the
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below divider reduces their incrementing frequency. */
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#define TIMER_DIVIDER_SHIFT 5
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#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
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/*
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* SoC-specific data.
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*/
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static void __iomem *timer_base, *local_base;
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static unsigned int timer_clk;
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static bool timer25Mhz = true;
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static u32 enable_mask;
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/*
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* Number of timer ticks per jiffy.
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*/
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static u32 ticks_per_jiffy;
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static struct clock_event_device __percpu *armada_370_xp_evt;
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static void local_timer_ctrl_clrset(u32 clr, u32 set)
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{
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writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
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local_base + TIMER_CTRL_OFF);
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}
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static u64 notrace armada_370_xp_read_sched_clock(void)
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{
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return ~readl(timer_base + TIMER0_VAL_OFF);
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}
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/*
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* Clockevent handling.
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*/
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static int
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armada_370_xp_clkevt_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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/*
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* Clear clockevent timer interrupt.
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*/
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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/*
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* Setup new clockevent timer value.
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*/
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writel(delta, local_base + TIMER0_VAL_OFF);
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/*
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* Enable the timer.
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*/
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local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
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return 0;
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}
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static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
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{
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/*
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* Disable timer.
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*/
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local_timer_ctrl_clrset(TIMER0_EN, 0);
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/*
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* ACK pending timer interrupt.
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*/
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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return 0;
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}
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static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
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{
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
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writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
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/*
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* Enable timer.
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*/
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local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
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return 0;
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}
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static int armada_370_xp_clkevt_irq;
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static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* ACK timer interrupt and call event handler.
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*/
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struct clock_event_device *evt = dev_id;
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writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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/*
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* Setup the local clock events for a CPU.
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*/
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static int armada_370_xp_timer_setup(struct clock_event_device *evt)
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{
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u32 clr = 0, set = 0;
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int cpu = smp_processor_id();
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if (timer25Mhz)
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set = TIMER0_25MHZ;
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else
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clr = TIMER0_25MHZ;
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local_timer_ctrl_clrset(clr, set);
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evt->name = "armada_370_xp_per_cpu_tick",
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evt->features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC;
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evt->shift = 32,
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evt->rating = 300,
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evt->set_next_event = armada_370_xp_clkevt_next_event,
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evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
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evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
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evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
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evt->tick_resume = armada_370_xp_clkevt_shutdown;
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evt->irq = armada_370_xp_clkevt_irq;
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evt->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
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enable_percpu_irq(evt->irq, 0);
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return 0;
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}
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static void armada_370_xp_timer_stop(struct clock_event_device *evt)
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{
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evt->set_state_shutdown(evt);
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disable_percpu_irq(evt->irq);
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}
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static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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/*
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* Grab cpu pointer in each case to avoid spurious
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* preemptible warnings
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*/
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
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break;
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case CPU_DYING:
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armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block armada_370_xp_timer_cpu_nb = {
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.notifier_call = armada_370_xp_timer_cpu_notify,
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};
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static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
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static int armada_370_xp_timer_suspend(void)
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{
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timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
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timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
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return 0;
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}
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static void armada_370_xp_timer_resume(void)
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{
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
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writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
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}
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struct syscore_ops armada_370_xp_timer_syscore_ops = {
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.suspend = armada_370_xp_timer_suspend,
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.resume = armada_370_xp_timer_resume,
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};
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static unsigned long armada_370_delay_timer_read(void)
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{
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return ~readl(timer_base + TIMER0_VAL_OFF);
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}
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static struct delay_timer armada_370_delay_timer = {
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.read_current_timer = armada_370_delay_timer_read,
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};
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static void __init armada_370_xp_timer_common_init(struct device_node *np)
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{
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u32 clr = 0, set = 0;
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int res;
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timer_base = of_iomap(np, 0);
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WARN_ON(!timer_base);
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local_base = of_iomap(np, 1);
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if (timer25Mhz) {
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set = TIMER0_25MHZ;
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enable_mask = TIMER0_EN;
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} else {
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clr = TIMER0_25MHZ;
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enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
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}
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atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
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local_timer_ctrl_clrset(clr, set);
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/*
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* We use timer 0 as clocksource, and private(local) timer 0
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* for clockevents
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*/
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armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
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ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled).
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*/
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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atomic_io_modify(timer_base + TIMER_CTRL_OFF,
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TIMER0_RELOAD_EN | enable_mask,
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TIMER0_RELOAD_EN | enable_mask);
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armada_370_delay_timer.freq = timer_clk;
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register_current_timer_delay(&armada_370_delay_timer);
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/*
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* Set scale and timer for sched_clock.
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*/
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sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
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clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
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"armada_370_xp_clocksource",
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timer_clk, 300, 32, clocksource_mmio_readl_down);
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register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
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armada_370_xp_evt = alloc_percpu(struct clock_event_device);
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/*
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* Setup clockevent timer (interrupt-driven).
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*/
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res = request_percpu_irq(armada_370_xp_clkevt_irq,
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armada_370_xp_timer_interrupt,
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"armada_370_xp_per_cpu_tick",
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armada_370_xp_evt);
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/* Immediately configure the timer on the boot CPU */
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if (!res)
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armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
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register_syscore_ops(&armada_370_xp_timer_syscore_ops);
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}
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static void __init armada_xp_timer_init(struct device_node *np)
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{
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struct clk *clk = of_clk_get_by_name(np, "fixed");
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/* The 25Mhz fixed clock is mandatory, and must always be available */
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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timer_clk = clk_get_rate(clk);
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armada_370_xp_timer_common_init(np);
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}
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CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
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armada_xp_timer_init);
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static void __init armada_375_timer_init(struct device_node *np)
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{
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struct clk *clk;
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clk = of_clk_get_by_name(np, "fixed");
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if (!IS_ERR(clk)) {
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clk_prepare_enable(clk);
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timer_clk = clk_get_rate(clk);
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} else {
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/*
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* This fallback is required in order to retain proper
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* devicetree backwards compatibility.
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*/
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clk = of_clk_get(np, 0);
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/* Must have at least a clock */
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
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timer25Mhz = false;
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}
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armada_370_xp_timer_common_init(np);
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}
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CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
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armada_375_timer_init);
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static void __init armada_370_timer_init(struct device_node *np)
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{
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struct clk *clk = of_clk_get(np, 0);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
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timer25Mhz = false;
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armada_370_xp_timer_common_init(np);
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}
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CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
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armada_370_timer_init);
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