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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
174 lines
6.4 KiB
C
174 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __TILCDC_REGS_H__
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#define __TILCDC_REGS_H__
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/* LCDC register definitions, based on da8xx-fb */
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#include <linux/bitops.h>
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#include "tilcdc_drv.h"
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/* LCDC Status Register */
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#define LCDC_END_OF_FRAME1 BIT(9)
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#define LCDC_END_OF_FRAME0 BIT(8)
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#define LCDC_PL_LOAD_DONE BIT(6)
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#define LCDC_FIFO_UNDERFLOW BIT(5)
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#define LCDC_SYNC_LOST BIT(2)
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#define LCDC_FRAME_DONE BIT(0)
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/* LCDC DMA Control Register */
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#define LCDC_DMA_BURST_SIZE(x) ((x) << 4)
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#define LCDC_DMA_BURST_SIZE_MASK ((0x7) << 4)
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#define LCDC_DMA_BURST_1 0x0
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#define LCDC_DMA_BURST_2 0x1
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#define LCDC_DMA_BURST_4 0x2
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#define LCDC_DMA_BURST_8 0x3
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#define LCDC_DMA_BURST_16 0x4
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#define LCDC_DMA_FIFO_THRESHOLD(x) ((x) << 8)
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#define LCDC_DMA_FIFO_THRESHOLD_MASK ((0x3) << 8)
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#define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2)
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#define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8)
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#define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9)
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#define LCDC_DUAL_FRAME_BUFFER_ENABLE BIT(0)
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/* LCDC Control Register */
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#define LCDC_CLK_DIVISOR(x) ((x) << 8)
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#define LCDC_CLK_DIVISOR_MASK ((0xFF) << 8)
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#define LCDC_RASTER_MODE 0x01
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/* LCDC Raster Control Register */
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#define LCDC_PALETTE_LOAD_MODE(x) ((x) << 20)
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#define LCDC_PALETTE_LOAD_MODE_MASK ((0x3) << 20)
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#define PALETTE_AND_DATA 0x00
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#define PALETTE_ONLY 0x01
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#define DATA_ONLY 0x02
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#define LCDC_MONO_8BIT_MODE BIT(9)
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#define LCDC_RASTER_ORDER BIT(8)
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#define LCDC_TFT_MODE BIT(7)
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#define LCDC_V1_UNDERFLOW_INT_ENA BIT(6)
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#define LCDC_V2_UNDERFLOW_INT_ENA BIT(5)
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#define LCDC_V1_PL_INT_ENA BIT(4)
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#define LCDC_V2_PL_INT_ENA BIT(6)
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#define LCDC_V1_SYNC_LOST_INT_ENA BIT(5)
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#define LCDC_V1_FRAME_DONE_INT_ENA BIT(3)
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#define LCDC_MONOCHROME_MODE BIT(1)
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#define LCDC_RASTER_ENABLE BIT(0)
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#define LCDC_TFT_ALT_ENABLE BIT(23)
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#define LCDC_STN_565_ENABLE BIT(24)
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#define LCDC_V2_DMA_CLK_EN BIT(2)
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#define LCDC_V2_LIDD_CLK_EN BIT(1)
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#define LCDC_V2_CORE_CLK_EN BIT(0)
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#define LCDC_V2_LPP_B10 26
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#define LCDC_V2_TFT_24BPP_MODE BIT(25)
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#define LCDC_V2_TFT_24BPP_UNPACK BIT(26)
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/* LCDC Raster Timing 2 Register */
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#define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
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#define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK ((0xF) << 16)
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#define LCDC_AC_BIAS_FREQUENCY(x) ((x) << 8)
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#define LCDC_AC_BIAS_FREQUENCY_MASK ((0xFF) << 8)
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#define LCDC_SYNC_CTRL BIT(25)
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#define LCDC_SYNC_EDGE BIT(24)
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#define LCDC_INVERT_PIXEL_CLOCK BIT(22)
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#define LCDC_INVERT_HSYNC BIT(21)
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#define LCDC_INVERT_VSYNC BIT(20)
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#define LCDC_LPP_B10 BIT(26)
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/* LCDC Block */
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#define LCDC_PID_REG 0x0
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#define LCDC_CTRL_REG 0x4
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#define LCDC_STAT_REG 0x8
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#define LCDC_RASTER_CTRL_REG 0x28
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#define LCDC_RASTER_TIMING_0_REG 0x2c
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#define LCDC_RASTER_TIMING_1_REG 0x30
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#define LCDC_RASTER_TIMING_2_REG 0x34
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#define LCDC_DMA_CTRL_REG 0x40
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#define LCDC_DMA_FB_BASE_ADDR_0_REG 0x44
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#define LCDC_DMA_FB_CEILING_ADDR_0_REG 0x48
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#define LCDC_DMA_FB_BASE_ADDR_1_REG 0x4c
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#define LCDC_DMA_FB_CEILING_ADDR_1_REG 0x50
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/* Interrupt Registers available only in Version 2 */
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#define LCDC_RAW_STAT_REG 0x58
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#define LCDC_MASKED_STAT_REG 0x5c
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#define LCDC_INT_ENABLE_SET_REG 0x60
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#define LCDC_INT_ENABLE_CLR_REG 0x64
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#define LCDC_END_OF_INT_IND_REG 0x68
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/* Clock registers available only on Version 2 */
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#define LCDC_CLK_ENABLE_REG 0x6c
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#define LCDC_CLK_RESET_REG 0x70
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#define LCDC_CLK_MAIN_RESET BIT(3)
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/*
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* Helpers:
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*/
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static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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iowrite32(data, priv->mmio + reg);
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}
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static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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volatile void __iomem *addr = priv->mmio + reg;
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#if defined(iowrite64) && !defined(iowrite64_is_nonatomic)
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iowrite64(data, addr);
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#else
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__iowmb();
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/* This compiles to strd (=64-bit write) on ARM7 */
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*(volatile u64 __force *)addr = __cpu_to_le64(data);
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#endif
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}
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static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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return ioread32(priv->mmio + reg);
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}
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static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg,
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u32 val, u32 mask)
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{
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tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));
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}
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static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
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{
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tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
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}
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static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
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{
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tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
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}
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/* the register to read/clear irqstatus differs between v1 and v2 of the IP */
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static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
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}
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static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
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{
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return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
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}
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static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
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{
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tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
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}
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#endif /* __TILCDC_REGS_H__ */
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