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https://github.com/edk2-porting/linux-next.git
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6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
375 lines
9.4 KiB
ArmAsm
375 lines
9.4 KiB
ArmAsm
/*
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* linux/arch/arm/mm/arm940.S: utility functions for ARM940T
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*
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
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#define CACHE_DLINESIZE 16
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#define CACHE_DSEGMENTS 4
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#define CACHE_DENTRIES 64
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.text
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/*
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* cpu_arm940_proc_init()
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* cpu_arm940_switch_mm()
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*
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* These are not required.
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*/
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ENTRY(cpu_arm940_proc_init)
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ENTRY(cpu_arm940_switch_mm)
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ret lr
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/*
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* cpu_arm940_proc_fin()
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*/
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ENTRY(cpu_arm940_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x00001000 @ i-cache
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bic r0, r0, #0x00000004 @ d-cache
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ret lr
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/*
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* cpu_arm940_reset(loc)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm940_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x00000005 @ .............c.p
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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ret r0
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ENDPROC(cpu_arm940_reset)
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.popsection
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/*
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* cpu_arm940_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm940_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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ret lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(arm940_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(arm940_flush_icache_all)
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/*
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* flush_user_cache_all()
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*/
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ENTRY(arm940_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm940_flush_kern_cache_all)
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mov r2, #VM_EXEC
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/* FALLTHROUGH */
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* There is no efficient way to flush a range of cache entries
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* in the specified address range. Thus, flushes all.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(arm940_flush_user_cache_range)
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mov ip, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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#else
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 3 to 0
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_user_range)
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/* FALLTHROUGH */
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(arm940_flush_kern_dcache_area)
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mov r0, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* There is no efficient way to invalidate a specifid virtual
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* address range. Thus, invalidates all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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arm940_dma_inv_range:
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* There is no efficient way to clean a specifid virtual
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* address range. Thus, cleans all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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arm940_dma_clean_range:
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ENTRY(cpu_arm940_dcache_clean_area)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_flush_range(start, end)
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*
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* There is no efficient way to clean and invalidate a specifid
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* virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_dma_flush_range)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
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#else
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mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
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#endif
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm940_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq arm940_dma_clean_range
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bcs arm940_dma_inv_range
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b arm940_dma_flush_range
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ENDPROC(arm940_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm940_dma_unmap_area)
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ret lr
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ENDPROC(arm940_dma_unmap_area)
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.globl arm940_flush_kern_cache_louis
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.equ arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions arm940
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.type __arm940_setup, #function
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__arm940_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
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mcr p15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c5, 0
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mcr p15, 0, r0, c6, c6, 0
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mcr p15, 0, r0, c6, c7, 0
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mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
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mcr p15, 0, r0, c6, c4, 1
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mcr p15, 0, r0, c6, c5, 1
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mcr p15, 0, r0, c6, c6, 1
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mcr p15, 0, r0, c6, c7, 1
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mov r0, #0x0000003F @ base = 0, size = 4GB
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mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
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mcr p15, 0, r0, c6, c0, 1
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
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mcr p15, 0, r0, c6, c1, 1
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
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mcr p15, 0, r0, c6, c2, 1
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
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mcr p15, 0, r0, c2, c0, 1
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #0x00 @ disable whole write buffer
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#else
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mov r0, #0x02 @ Region 1 write bufferred
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#endif
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mcr p15, 0, r0, c3, c0, 0
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mov r0, #0x10000
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sub r0, r0, #1 @ r0 = 0xffff
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mcr p15, 0, r0, c5, c0, 0 @ all read/write access
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mcr p15, 0, r0, c5, c0, 1
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mrc p15, 0, r0, c1, c0 @ get control register
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orr r0, r0, #0x00001000 @ I-cache
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orr r0, r0, #0x00000005 @ MPU/D-cache
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ret lr
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.size __arm940_setup, . - __arm940_setup
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions arm940, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
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.section ".rodata"
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string cpu_arch_name, "armv4t"
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string cpu_elf_name, "v4"
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string cpu_arm940_name, "ARM940T"
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm940_proc_info,#object
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__arm940_proc_info:
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.long 0x41009400
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.long 0xff00fff0
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.long 0
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b __arm940_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
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.long cpu_arm940_name
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.long arm940_processor_functions
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.long 0
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.long 0
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.long arm940_cache_fns
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.size __arm940_proc_info, . - __arm940_proc_info
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