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a0b89872b3
The firmware may have been updated, in which case, it's the same device, and in that case, we do not want to remove and add the device, we want to let it continue as is. Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
361 lines
9.8 KiB
C
361 lines
9.8 KiB
C
/*
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* Disk Array driver for HP Smart Array SAS controllers
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* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Questions/Comments/Bugfixes to iss_storagedev@hp.com
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*
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*/
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#ifndef HPSA_H
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#define HPSA_H
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#include <scsi/scsicam.h>
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#define IO_OK 0
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#define IO_ERROR 1
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struct ctlr_info;
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struct access_method {
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void (*submit_command)(struct ctlr_info *h,
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struct CommandList *c);
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void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
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unsigned long (*fifo_full)(struct ctlr_info *h);
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bool (*intr_pending)(struct ctlr_info *h);
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unsigned long (*command_completed)(struct ctlr_info *h);
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};
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struct hpsa_scsi_dev_t {
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int devtype;
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int bus, target, lun; /* as presented to the OS */
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unsigned char scsi3addr[8]; /* as presented to the HW */
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#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
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unsigned char device_id[16]; /* from inquiry pg. 0x83 */
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unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
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unsigned char model[16]; /* bytes 16-31 of inquiry data */
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unsigned char raid_level; /* from inquiry page 0xC1 */
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};
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struct ctlr_info {
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int ctlr;
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char devname[8];
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char *product_name;
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struct pci_dev *pdev;
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u32 board_id;
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void __iomem *vaddr;
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unsigned long paddr;
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int nr_cmds; /* Number of commands allowed on this controller */
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struct CfgTable __iomem *cfgtable;
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int max_sg_entries;
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int interrupts_enabled;
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int major;
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int max_commands;
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int commands_outstanding;
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int max_outstanding; /* Debug */
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int usage_count; /* number of opens all all minor devices */
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# define PERF_MODE_INT 0
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# define DOORBELL_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[4];
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unsigned int msix_vector;
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unsigned int msi_vector;
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struct access_method access;
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/* queue and queue Info */
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struct hlist_head reqQ;
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struct hlist_head cmpQ;
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unsigned int Qdepth;
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unsigned int maxQsinceinit;
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unsigned int maxSG;
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spinlock_t lock;
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int maxsgentries;
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u8 max_cmd_sg_entries;
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int chainsize;
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struct SGDescriptor **cmd_sg_list;
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/* pointers to command and error info pool */
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struct CommandList *cmd_pool;
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dma_addr_t cmd_pool_dhandle;
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struct ErrorInfo *errinfo_pool;
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dma_addr_t errinfo_pool_dhandle;
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unsigned long *cmd_pool_bits;
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int nr_allocs;
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int nr_frees;
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int busy_initializing;
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int busy_scanning;
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int scan_finished;
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spinlock_t scan_lock;
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wait_queue_head_t scan_wait_queue;
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struct Scsi_Host *scsi_host;
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spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
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int ndevices; /* number of used elements in .dev[] array. */
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#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
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struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
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/*
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* Performant mode tables.
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*/
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u32 trans_support;
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u32 trans_offset;
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struct TransTable_struct *transtable;
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unsigned long transMethod;
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/*
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* Performant mode completion buffer
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*/
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u64 *reply_pool;
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dma_addr_t reply_pool_dhandle;
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u64 *reply_pool_head;
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size_t reply_pool_size;
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unsigned char reply_pool_wraparound;
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u32 *blockFetchTable;
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unsigned char *hba_inquiry_data;
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};
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#define HPSA_ABORT_MSG 0
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#define HPSA_DEVICE_RESET_MSG 1
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#define HPSA_BUS_RESET_MSG 2
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#define HPSA_HOST_RESET_MSG 3
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#define HPSA_MSG_SEND_RETRY_LIMIT 10
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#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
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/* Maximum time in seconds driver will wait for command completions
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* when polling before giving up.
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*/
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#define HPSA_MAX_POLL_TIME_SECS (20)
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/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
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* how many times to retry TEST UNIT READY on a device
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* while waiting for it to become ready before giving up.
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* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
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* between sending TURs while waiting for a device
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* to become ready.
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*/
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#define HPSA_TUR_RETRY_LIMIT (20)
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#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
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/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
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* to become ready, in seconds, before giving up on it.
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* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
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* between polling the board to see if it is ready, in
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* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
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* HPSA_BOARD_READY_ITERATIONS are derived from those.
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*/
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#define HPSA_BOARD_READY_WAIT_SECS (120)
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#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
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#define HPSA_BOARD_READY_POLL_INTERVAL \
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((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
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#define HPSA_BOARD_READY_ITERATIONS \
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((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
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HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
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#define HPSA_POST_RESET_PAUSE_MSECS (3000)
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#define HPSA_POST_RESET_NOOP_RETRIES (12)
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/* Defining the diffent access_menthods */
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/*
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* Memory mapped FIFO interface (SMART 53xx cards)
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*/
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#define SA5_DOORBELL 0x20
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#define SA5_REQUEST_PORT_OFFSET 0x40
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#define SA5_REPLY_INTR_MASK_OFFSET 0x34
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#define SA5_REPLY_PORT_OFFSET 0x44
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#define SA5_INTR_STATUS 0x30
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#define SA5_SCRATCHPAD_OFFSET 0xB0
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#define SA5_CTCFG_OFFSET 0xB4
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#define SA5_CTMEM_OFFSET 0xB8
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#define SA5_INTR_OFF 0x08
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#define SA5B_INTR_OFF 0x04
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#define SA5_INTR_PENDING 0x08
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#define SA5B_INTR_PENDING 0x04
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#define FIFO_EMPTY 0xffffffff
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#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
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#define HPSA_ERROR_BIT 0x02
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/* Performant mode flags */
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#define SA5_PERF_INTR_PENDING 0x04
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#define SA5_PERF_INTR_OFF 0x05
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#define SA5_OUTDB_STATUS_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR 0xA0
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_STATUS 0x9C
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#define HPSA_INTR_ON 1
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#define HPSA_INTR_OFF 0
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/*
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Send the command to the hardware
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*/
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static void SA5_submit_command(struct ctlr_info *h,
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struct CommandList *c)
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{
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dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
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c->Header.Tag.lower);
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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h->commands_outstanding++;
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if (h->commands_outstanding > h->max_outstanding)
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h->max_outstanding = h->commands_outstanding;
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}
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/*
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* This card is the opposite of the other cards.
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* 0 turns interrupts on...
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* 0x08 turns them off...
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*/
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static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else { /* Turn them off */
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h->interrupts_enabled = 0;
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writel(SA5_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* turn on interrupts */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else {
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h->interrupts_enabled = 0;
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writel(SA5_PERF_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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static unsigned long SA5_performant_completed(struct ctlr_info *h)
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{
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unsigned long register_value = FIFO_EMPTY;
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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/* msi auto clears the interrupt pending bit. */
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if (!(h->msi_vector || h->msix_vector)) {
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writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
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/* Do a read in order to flush the write to the controller
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* (as per spec.)
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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}
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if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
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register_value = *(h->reply_pool_head);
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(h->reply_pool_head)++;
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h->commands_outstanding--;
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} else {
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register_value = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
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h->reply_pool_head = h->reply_pool;
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h->reply_pool_wraparound ^= 1;
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}
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return register_value;
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}
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/*
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* Returns true if fifo is full.
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*
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*/
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static unsigned long SA5_fifo_full(struct ctlr_info *h)
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{
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if (h->commands_outstanding >= h->max_commands)
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return 1;
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else
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return 0;
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}
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/*
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* returns value read from hardware.
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* returns FIFO_EMPTY if there is nothing to read
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*/
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static unsigned long SA5_completed(struct ctlr_info *h)
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{
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unsigned long register_value
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= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
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if (register_value != FIFO_EMPTY)
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h->commands_outstanding--;
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#ifdef HPSA_DEBUG
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if (register_value != FIFO_EMPTY)
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dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
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register_value);
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else
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dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
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#endif
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return register_value;
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}
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/*
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* Returns true if an interrupt is pending..
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*/
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static bool SA5_intr_pending(struct ctlr_info *h)
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{
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unsigned long register_value =
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readl(h->vaddr + SA5_INTR_STATUS);
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dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
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return register_value & SA5_INTR_PENDING;
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}
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static bool SA5_performant_intr_pending(struct ctlr_info *h)
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{
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unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
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if (!register_value)
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return false;
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if (h->msi_vector || h->msix_vector)
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return true;
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/* Read outbound doorbell to flush */
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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return register_value & SA5_OUTDB_STATUS_PERF_BIT;
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}
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static struct access_method SA5_access = {
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SA5_submit_command,
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SA5_intr_mask,
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SA5_fifo_full,
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SA5_intr_pending,
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SA5_completed,
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};
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static struct access_method SA5_performant_access = {
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SA5_submit_command,
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SA5_performant_intr_mask,
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SA5_fifo_full,
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SA5_performant_intr_pending,
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SA5_performant_completed,
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};
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struct board_type {
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u32 board_id;
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char *product_name;
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struct access_method *access;
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};
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#endif /* HPSA_H */
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