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cb646e2b02
This patch adds support for the PTP clock found on the DP83640. The basic clock operations and one external time stamp have been implemented. Signed-off-by: Richard Cochran <richard.cochran@omicron.at> Signed-off-by: John Stultz <john.stultz@linaro.org>
268 lines
16 KiB
C
268 lines
16 KiB
C
/* dp83640_reg.h
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* Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
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*/
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#ifndef HAVE_DP83640_REGISTERS
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#define HAVE_DP83640_REGISTERS
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#define PAGE0 0x0000
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#define PHYCR2 0x001c /* PHY Control Register 2 */
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#define PAGE4 0x0004
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#define PTP_CTL 0x0014 /* PTP Control Register */
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#define PTP_TDR 0x0015 /* PTP Time Data Register */
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#define PTP_STS 0x0016 /* PTP Status Register */
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#define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
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#define PTP_RATEL 0x0018 /* PTP Rate Low Register */
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#define PTP_RATEH 0x0019 /* PTP Rate High Register */
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#define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
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#define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
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#define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
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#define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
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#define PTP_ESTS 0x001e /* PTP Event Status Register */
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#define PTP_EDATA 0x001f /* PTP Event Data Register */
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#define PAGE5 0x0005
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#define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
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#define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
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#define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
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#define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
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#define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
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#define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
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#define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
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#define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
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#define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
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#define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
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#define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
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#define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
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#define PAGE6 0x0006
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#define PTP_COC 0x0014 /* PTP Clock Output Control Register */
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#define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
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#define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
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#define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
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#define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
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#define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
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#define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
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#define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
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#define PTP_ETR 0x001c /* PTP Ethernet Type Register */
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#define PTP_OFF 0x001d /* PTP Offset Register */
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#define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
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#define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
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/* Bit definitions for the PHYCR2 register */
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#define BC_WRITE (1<<11) /* Broadcast Write Enable */
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/* Bit definitions for the PTP_CTL register */
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#define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
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#define TRIG_SEL_MASK (0x7)
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#define TRIG_DIS (1<<9) /* Disable PTP Trigger */
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#define TRIG_EN (1<<8) /* Enable PTP Trigger */
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#define TRIG_READ (1<<7) /* Read PTP Trigger */
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#define TRIG_LOAD (1<<6) /* Load PTP Trigger */
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#define PTP_RD_CLK (1<<5) /* Read PTP Clock */
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#define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
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#define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
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#define PTP_ENABLE (1<<2) /* Enable PTP Clock */
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#define PTP_DISABLE (1<<1) /* Disable PTP Clock */
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#define PTP_RESET (1<<0) /* Reset PTP Clock */
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/* Bit definitions for the PTP_STS register */
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#define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
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#define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
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#define TRIG_DONE (1<<9) /* PTP Trigger Done */
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#define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
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#define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
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#define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
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#define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
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#define EVENT_IE (1<<0) /* Event Interrupt Enable */
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/* Bit definitions for the PTP_TSTS register */
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#define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
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#define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
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#define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
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#define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
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#define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
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#define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
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#define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
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#define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
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#define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
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#define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
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#define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
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#define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
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#define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
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#define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
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#define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
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#define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
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/* Bit definitions for the PTP_RATEH register */
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#define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
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#define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
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#define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
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#define PTP_RATE_HI_MASK (0x3ff)
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/* Bit definitions for the PTP_ESTS register */
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#define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
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#define EVNTS_MISSED_MASK (0x7)
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#define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
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#define EVNT_TS_LEN_MASK (0x3)
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#define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
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#define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
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#define EVNT_NUM_MASK (0x7)
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#define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
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#define EVENT_DET (1<<0) /* PTP Event Detected */
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/* Bit definitions for the PTP_EDATA register */
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#define E7_RISE (1<<15) /* Indicates direction of Event 7 */
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#define E7_DET (1<<14) /* Indicates Event 7 detected */
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#define E6_RISE (1<<13) /* Indicates direction of Event 6 */
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#define E6_DET (1<<12) /* Indicates Event 6 detected */
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#define E5_RISE (1<<11) /* Indicates direction of Event 5 */
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#define E5_DET (1<<10) /* Indicates Event 5 detected */
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#define E4_RISE (1<<9) /* Indicates direction of Event 4 */
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#define E4_DET (1<<8) /* Indicates Event 4 detected */
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#define E3_RISE (1<<7) /* Indicates direction of Event 3 */
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#define E3_DET (1<<6) /* Indicates Event 3 detected */
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#define E2_RISE (1<<5) /* Indicates direction of Event 2 */
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#define E2_DET (1<<4) /* Indicates Event 2 detected */
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#define E1_RISE (1<<3) /* Indicates direction of Event 1 */
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#define E1_DET (1<<2) /* Indicates Event 1 detected */
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#define E0_RISE (1<<1) /* Indicates direction of Event 0 */
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#define E0_DET (1<<0) /* Indicates Event 0 detected */
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/* Bit definitions for the PTP_TRIG register */
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#define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
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#define TRIG_PER (1<<14) /* generate a periodic signal */
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#define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
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#define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
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#define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
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#define TRIG_GPIO_MASK (0xf)
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#define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
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#define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
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#define TRIG_CSEL_MASK (0x7)
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#define TRIG_WR (1<<0) /* Trigger Configuration Write */
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/* Bit definitions for the PTP_EVNT register */
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#define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
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#define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
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#define EVNT_SINGLE (1<<12) /* enable single event capture operation */
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#define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
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#define EVNT_GPIO_MASK (0xf)
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#define EVNT_SEL_SHIFT (1) /* Event Select */
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#define EVNT_SEL_MASK (0x7)
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#define EVNT_WR (1<<0) /* Event Configuration Write */
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/* Bit definitions for the PTP_TXCFG0 register */
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#define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
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#define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
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#define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
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#define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
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#define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
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#define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
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#define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
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#define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
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#define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
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#define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
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#define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
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#define TX_PTP_VER_MASK (0xf)
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#define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
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/* Bit definitions for the PTP_TXCFG1 register */
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#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
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#define BYTE0_MASK_MASK (0xff)
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#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
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#define BYTE0_DATA_MASK (0xff)
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/* Bit definitions for the PSF_CFG0 register */
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#define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
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#define MAC_SRC_ADD_MASK (0x3)
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#define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
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#define MIN_PRE_MASK (0x7)
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#define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
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#define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
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#define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
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#define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
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#define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
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#define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
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#define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
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#define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
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/* Bit definitions for the PTP_RXCFG0 register */
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#define DOMAIN_EN (1<<15) /* Domain Match Enable */
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#define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
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#define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
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#define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
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#define RX_SLAVE (1<<11) /* Receive Slave Only */
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#define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
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#define IP1588_EN_MASK (0xf)
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#define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
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#define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
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#define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
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#define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
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#define RX_PTP_VER_MASK (0xf)
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#define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
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/* Bit definitions for the PTP_RXCFG1 register */
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#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
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#define BYTE0_MASK_MASK (0xff)
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#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
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#define BYTE0_DATA_MASK (0xff)
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/* Bit definitions for the PTP_RXCFG3 register */
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#define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
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#define TS_MIN_IFG_MASK (0xf)
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#define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
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#define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
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#define TS_APPEND (1<<9) /* Append Timestamp for L2 */
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#define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
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#define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
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#define PTP_DOMAIN_MASK (0xff)
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/* Bit definitions for the PTP_RXCFG4 register */
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#define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
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#define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
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#define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
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#define TS_SEC_LEN_MASK (0x3)
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#define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
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#define RXTS_NS_OFF_MASK (0x3f)
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#define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
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#define RXTS_SEC_OFF_MASK (0x3f)
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/* Bit definitions for the PTP_COC register */
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#define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
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#define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
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#define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
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#define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
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#define PTP_CLKDIV_MASK (0xff)
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/* Bit definitions for the PSF_CFG1 register */
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#define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
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#define PTPRESERVED_MASK (0xf)
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#define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
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#define VERSIONPTP_MASK (0xf)
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#define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
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#define TRANSPORT_SPECIFIC_MASK (0xf)
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#define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
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#define MESSAGETYPE_MASK (0xf)
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/* Bit definitions for the PTP_SFDCFG register */
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#define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
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#define TX_SFD_GPIO_MASK (0xf)
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#define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
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#define RX_SFD_GPIO_MASK (0xf)
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/* Bit definitions for the PTP_INTCTL register */
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#define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
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#define PTP_INT_GPIO_MASK (0xf)
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/* Bit definitions for the PTP_CLKSRC register */
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#define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
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#define CLK_SRC_MASK (0x3)
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#define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
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#define CLK_SRC_PER_MASK (0x7f)
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/* Bit definitions for the PTP_OFF register */
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#define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
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#define PTP_OFFSET_MASK (0xff)
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#endif
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