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ffe6c42aa3
It's been unused for ages, and contains bugs (e.g. incorrect shifts in lsl64()). Reported-by: Jonathan Elchison <jelchison@gmail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
290 lines
8.8 KiB
C
290 lines
8.8 KiB
C
/* multi_arith.h: multi-precision integer arithmetic functions, needed
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to do extended-precision floating point.
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(c) 1998 David Huggins-Daines.
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Somewhat based on arch/alpha/math-emu/ieee-math.c, which is (c)
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David Mosberger-Tang.
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You may copy, modify, and redistribute this file under the terms of
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the GNU General Public License, version 2, or any later version, at
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your convenience. */
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/* Note:
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These are not general multi-precision math routines. Rather, they
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implement the subset of integer arithmetic that we need in order to
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multiply, divide, and normalize 128-bit unsigned mantissae. */
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#ifndef MULTI_ARITH_H
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#define MULTI_ARITH_H
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static inline void fp_denormalize(struct fp_ext *reg, unsigned int cnt)
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{
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reg->exp += cnt;
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switch (cnt) {
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case 0 ... 8:
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reg->lowmant = reg->mant.m32[1] << (8 - cnt);
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reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) |
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(reg->mant.m32[0] << (32 - cnt));
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reg->mant.m32[0] = reg->mant.m32[0] >> cnt;
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break;
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case 9 ... 32:
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reg->lowmant = reg->mant.m32[1] >> (cnt - 8);
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if (reg->mant.m32[1] << (40 - cnt))
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reg->lowmant |= 1;
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reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) |
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(reg->mant.m32[0] << (32 - cnt));
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reg->mant.m32[0] = reg->mant.m32[0] >> cnt;
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break;
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case 33 ... 39:
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asm volatile ("bfextu %1{%2,#8},%0" : "=d" (reg->lowmant)
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: "m" (reg->mant.m32[0]), "d" (64 - cnt));
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if (reg->mant.m32[1] << (40 - cnt))
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reg->lowmant |= 1;
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reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32);
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reg->mant.m32[0] = 0;
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break;
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case 40 ... 71:
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reg->lowmant = reg->mant.m32[0] >> (cnt - 40);
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if ((reg->mant.m32[0] << (72 - cnt)) || reg->mant.m32[1])
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reg->lowmant |= 1;
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reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32);
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reg->mant.m32[0] = 0;
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break;
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default:
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reg->lowmant = reg->mant.m32[0] || reg->mant.m32[1];
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reg->mant.m32[0] = 0;
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reg->mant.m32[1] = 0;
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break;
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}
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}
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static inline int fp_overnormalize(struct fp_ext *reg)
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{
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int shift;
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if (reg->mant.m32[0]) {
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asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[0]));
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reg->mant.m32[0] = (reg->mant.m32[0] << shift) | (reg->mant.m32[1] >> (32 - shift));
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reg->mant.m32[1] = (reg->mant.m32[1] << shift);
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} else {
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asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[1]));
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reg->mant.m32[0] = (reg->mant.m32[1] << shift);
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reg->mant.m32[1] = 0;
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shift += 32;
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}
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return shift;
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}
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static inline int fp_addmant(struct fp_ext *dest, struct fp_ext *src)
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{
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int carry;
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/* we assume here, gcc only insert move and a clr instr */
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asm volatile ("add.b %1,%0" : "=d,g" (dest->lowmant)
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: "g,d" (src->lowmant), "0,0" (dest->lowmant));
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asm volatile ("addx.l %1,%0" : "=d" (dest->mant.m32[1])
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: "d" (src->mant.m32[1]), "0" (dest->mant.m32[1]));
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asm volatile ("addx.l %1,%0" : "=d" (dest->mant.m32[0])
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: "d" (src->mant.m32[0]), "0" (dest->mant.m32[0]));
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asm volatile ("addx.l %0,%0" : "=d" (carry) : "0" (0));
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return carry;
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}
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static inline int fp_addcarry(struct fp_ext *reg)
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{
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if (++reg->exp == 0x7fff) {
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if (reg->mant.m64)
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fp_set_sr(FPSR_EXC_INEX2);
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reg->mant.m64 = 0;
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fp_set_sr(FPSR_EXC_OVFL);
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return 0;
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}
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reg->lowmant = (reg->mant.m32[1] << 7) | (reg->lowmant ? 1 : 0);
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reg->mant.m32[1] = (reg->mant.m32[1] >> 1) |
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(reg->mant.m32[0] << 31);
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reg->mant.m32[0] = (reg->mant.m32[0] >> 1) | 0x80000000;
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return 1;
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}
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static inline void fp_submant(struct fp_ext *dest, struct fp_ext *src1,
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struct fp_ext *src2)
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{
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/* we assume here, gcc only insert move and a clr instr */
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asm volatile ("sub.b %1,%0" : "=d,g" (dest->lowmant)
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: "g,d" (src2->lowmant), "0,0" (src1->lowmant));
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asm volatile ("subx.l %1,%0" : "=d" (dest->mant.m32[1])
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: "d" (src2->mant.m32[1]), "0" (src1->mant.m32[1]));
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asm volatile ("subx.l %1,%0" : "=d" (dest->mant.m32[0])
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: "d" (src2->mant.m32[0]), "0" (src1->mant.m32[0]));
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}
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#define fp_mul64(desth, destl, src1, src2) ({ \
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asm ("mulu.l %2,%1:%0" : "=d" (destl), "=d" (desth) \
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: "dm" (src1), "0" (src2)); \
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})
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#define fp_div64(quot, rem, srch, srcl, div) \
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asm ("divu.l %2,%1:%0" : "=d" (quot), "=d" (rem) \
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: "dm" (div), "1" (srch), "0" (srcl))
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#define fp_add64(dest1, dest2, src1, src2) ({ \
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asm ("add.l %1,%0" : "=d,dm" (dest2) \
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: "dm,d" (src2), "0,0" (dest2)); \
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asm ("addx.l %1,%0" : "=d" (dest1) \
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: "d" (src1), "0" (dest1)); \
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})
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#define fp_addx96(dest, src) ({ \
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/* we assume here, gcc only insert move and a clr instr */ \
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asm volatile ("add.l %1,%0" : "=d,g" (dest->m32[2]) \
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: "g,d" (temp.m32[1]), "0,0" (dest->m32[2])); \
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asm volatile ("addx.l %1,%0" : "=d" (dest->m32[1]) \
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: "d" (temp.m32[0]), "0" (dest->m32[1])); \
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asm volatile ("addx.l %1,%0" : "=d" (dest->m32[0]) \
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: "d" (0), "0" (dest->m32[0])); \
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})
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#define fp_sub64(dest, src) ({ \
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asm ("sub.l %1,%0" : "=d,dm" (dest.m32[1]) \
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: "dm,d" (src.m32[1]), "0,0" (dest.m32[1])); \
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asm ("subx.l %1,%0" : "=d" (dest.m32[0]) \
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: "d" (src.m32[0]), "0" (dest.m32[0])); \
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})
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#define fp_sub96c(dest, srch, srcm, srcl) ({ \
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char carry; \
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asm ("sub.l %1,%0" : "=d,dm" (dest.m32[2]) \
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: "dm,d" (srcl), "0,0" (dest.m32[2])); \
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asm ("subx.l %1,%0" : "=d" (dest.m32[1]) \
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: "d" (srcm), "0" (dest.m32[1])); \
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asm ("subx.l %2,%1; scs %0" : "=d" (carry), "=d" (dest.m32[0]) \
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: "d" (srch), "1" (dest.m32[0])); \
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carry; \
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})
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static inline void fp_multiplymant(union fp_mant128 *dest, struct fp_ext *src1,
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struct fp_ext *src2)
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{
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union fp_mant64 temp;
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fp_mul64(dest->m32[0], dest->m32[1], src1->mant.m32[0], src2->mant.m32[0]);
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fp_mul64(dest->m32[2], dest->m32[3], src1->mant.m32[1], src2->mant.m32[1]);
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fp_mul64(temp.m32[0], temp.m32[1], src1->mant.m32[0], src2->mant.m32[1]);
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fp_addx96(dest, temp);
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fp_mul64(temp.m32[0], temp.m32[1], src1->mant.m32[1], src2->mant.m32[0]);
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fp_addx96(dest, temp);
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}
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static inline void fp_dividemant(union fp_mant128 *dest, struct fp_ext *src,
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struct fp_ext *div)
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{
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union fp_mant128 tmp;
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union fp_mant64 tmp64;
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unsigned long *mantp = dest->m32;
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unsigned long fix, rem, first, dummy;
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int i;
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/* the algorithm below requires dest to be smaller than div,
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but both have the high bit set */
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if (src->mant.m64 >= div->mant.m64) {
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fp_sub64(src->mant, div->mant);
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*mantp = 1;
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} else
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*mantp = 0;
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mantp++;
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/* basic idea behind this algorithm: we can't divide two 64bit numbers
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(AB/CD) directly, but we can calculate AB/C0, but this means this
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quotient is off by C0/CD, so we have to multiply the first result
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to fix the result, after that we have nearly the correct result
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and only a few corrections are needed. */
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/* C0/CD can be precalculated, but it's an 64bit division again, but
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we can make it a bit easier, by dividing first through C so we get
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10/1D and now only a single shift and the value fits into 32bit. */
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fix = 0x80000000;
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dummy = div->mant.m32[1] / div->mant.m32[0] + 1;
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dummy = (dummy >> 1) | fix;
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fp_div64(fix, dummy, fix, 0, dummy);
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fix--;
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for (i = 0; i < 3; i++, mantp++) {
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if (src->mant.m32[0] == div->mant.m32[0]) {
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fp_div64(first, rem, 0, src->mant.m32[1], div->mant.m32[0]);
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fp_mul64(*mantp, dummy, first, fix);
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*mantp += fix;
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} else {
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fp_div64(first, rem, src->mant.m32[0], src->mant.m32[1], div->mant.m32[0]);
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fp_mul64(*mantp, dummy, first, fix);
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}
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fp_mul64(tmp.m32[0], tmp.m32[1], div->mant.m32[0], first - *mantp);
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fp_add64(tmp.m32[0], tmp.m32[1], 0, rem);
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tmp.m32[2] = 0;
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fp_mul64(tmp64.m32[0], tmp64.m32[1], *mantp, div->mant.m32[1]);
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fp_sub96c(tmp, 0, tmp64.m32[0], tmp64.m32[1]);
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src->mant.m32[0] = tmp.m32[1];
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src->mant.m32[1] = tmp.m32[2];
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while (!fp_sub96c(tmp, 0, div->mant.m32[0], div->mant.m32[1])) {
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src->mant.m32[0] = tmp.m32[1];
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src->mant.m32[1] = tmp.m32[2];
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*mantp += 1;
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}
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}
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}
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static inline void fp_putmant128(struct fp_ext *dest, union fp_mant128 *src,
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int shift)
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{
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unsigned long tmp;
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switch (shift) {
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case 0:
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dest->mant.m64 = src->m64[0];
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dest->lowmant = src->m32[2] >> 24;
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if (src->m32[3] || (src->m32[2] << 8))
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dest->lowmant |= 1;
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break;
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case 1:
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asm volatile ("lsl.l #1,%0"
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: "=d" (tmp) : "0" (src->m32[2]));
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asm volatile ("roxl.l #1,%0"
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: "=d" (dest->mant.m32[1]) : "0" (src->m32[1]));
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asm volatile ("roxl.l #1,%0"
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: "=d" (dest->mant.m32[0]) : "0" (src->m32[0]));
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dest->lowmant = tmp >> 24;
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if (src->m32[3] || (tmp << 8))
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dest->lowmant |= 1;
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break;
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case 31:
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asm volatile ("lsr.l #1,%1; roxr.l #1,%0"
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: "=d" (dest->mant.m32[0])
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: "d" (src->m32[0]), "0" (src->m32[1]));
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asm volatile ("roxr.l #1,%0"
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: "=d" (dest->mant.m32[1]) : "0" (src->m32[2]));
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asm volatile ("roxr.l #1,%0"
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: "=d" (tmp) : "0" (src->m32[3]));
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dest->lowmant = tmp >> 24;
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if (src->m32[3] << 7)
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dest->lowmant |= 1;
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break;
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case 32:
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dest->mant.m32[0] = src->m32[1];
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dest->mant.m32[1] = src->m32[2];
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dest->lowmant = src->m32[3] >> 24;
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if (src->m32[3] << 8)
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dest->lowmant |= 1;
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break;
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}
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}
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#endif /* MULTI_ARITH_H */
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