Dinh Nguyen 8c489216c3 clk: socfpga: arria10: convert to use clk_hw ... As recommended by Stephen Boyd, convert the Arria10 clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-03-30 19:26:26 -07:00
..
clk-agilex.c	clk: socfpga: agilex: add clock driver for eASIC N5X platform	2021-02-12 13:04:58 -08:00
clk-gate-a10.c	clk: socfpga: arria10: convert to use clk_hw	2021-03-30 19:26:26 -07:00
clk-gate-s10.c	clk: socfpga: stratix10: use new parent data scheme	2020-05-26 19:13:05 -07:00
clk-gate.c	clk: socfpga: use clk_hw_register for a5/c5	2021-03-30 19:26:26 -07:00
clk-periph-a10.c	clk: socfpga: arria10: convert to use clk_hw	2021-03-30 19:26:26 -07:00
clk-periph-s10.c	clk: socfpga: agilex: add clock driver for eASIC N5X platform	2021-02-12 13:04:58 -08:00
clk-periph.c	clk: socfpga: use clk_hw_register for a5/c5	2021-03-30 19:26:26 -07:00
clk-pll-a10.c	clk: socfpga: arria10: convert to use clk_hw	2021-03-30 19:26:26 -07:00
clk-pll-s10.c	clk: socfpga: agilex: add clock driver for eASIC N5X platform	2021-02-12 13:04:58 -08:00
clk-pll.c	clk: socfpga: use clk_hw_register for a5/c5	2021-03-30 19:26:26 -07:00
clk-s10.c	clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk	2020-09-22 12:54:41 -07:00
clk.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13	2019-05-21 11:28:45 +02:00
clk.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
Makefile	clk: socfpga: agilex: add clock driver for the Agilex platform	2020-05-26 19:13:05 -07:00
stratix10-clk.h	clk: socfpga: agilex: add clock driver for eASIC N5X platform	2021-02-12 13:04:58 -08:00