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9bd568a50c
Enforce all device constraints on the descriptor memory region. There are several constraints on the descriptor memory, as documented in the specification. The current code does not enforce them and/or incorrectly enforces them. Those constraints are: - The address limitations on 30/32bit engines, that also apply to the skbs. - The 4k alignment requirement on 30/32bit engines. - The 8k alignment requirement on 64bit engines. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
296 lines
9.5 KiB
C
296 lines
9.5 KiB
C
#ifndef B43_DMA_H_
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#define B43_DMA_H_
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#include <linux/ieee80211.h>
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#include "b43.h"
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/* DMA-Interrupt reasons. */
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#define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
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| (1 << 14) | (1 << 15))
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#define B43_DMAIRQ_NONFATALMASK (1 << 13)
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#define B43_DMAIRQ_RX_DONE (1 << 16)
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/*** 32-bit DMA Engine. ***/
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/* 32-bit DMA controller registers. */
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#define B43_DMA32_TXCTL 0x00
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#define B43_DMA32_TXENABLE 0x00000001
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#define B43_DMA32_TXSUSPEND 0x00000002
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#define B43_DMA32_TXLOOPBACK 0x00000004
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#define B43_DMA32_TXFLUSH 0x00000010
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#define B43_DMA32_TXADDREXT_MASK 0x00030000
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#define B43_DMA32_TXADDREXT_SHIFT 16
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#define B43_DMA32_TXRING 0x04
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#define B43_DMA32_TXINDEX 0x08
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#define B43_DMA32_TXSTATUS 0x0C
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#define B43_DMA32_TXDPTR 0x00000FFF
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#define B43_DMA32_TXSTATE 0x0000F000
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#define B43_DMA32_TXSTAT_DISABLED 0x00000000
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#define B43_DMA32_TXSTAT_ACTIVE 0x00001000
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#define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000
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#define B43_DMA32_TXSTAT_STOPPED 0x00003000
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#define B43_DMA32_TXSTAT_SUSP 0x00004000
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#define B43_DMA32_TXERROR 0x000F0000
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#define B43_DMA32_TXERR_NOERR 0x00000000
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#define B43_DMA32_TXERR_PROT 0x00010000
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#define B43_DMA32_TXERR_UNDERRUN 0x00020000
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#define B43_DMA32_TXERR_BUFREAD 0x00030000
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#define B43_DMA32_TXERR_DESCREAD 0x00040000
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#define B43_DMA32_TXACTIVE 0xFFF00000
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#define B43_DMA32_RXCTL 0x10
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#define B43_DMA32_RXENABLE 0x00000001
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#define B43_DMA32_RXFROFF_MASK 0x000000FE
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#define B43_DMA32_RXFROFF_SHIFT 1
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#define B43_DMA32_RXDIRECTFIFO 0x00000100
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#define B43_DMA32_RXADDREXT_MASK 0x00030000
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#define B43_DMA32_RXADDREXT_SHIFT 16
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#define B43_DMA32_RXRING 0x14
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#define B43_DMA32_RXINDEX 0x18
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#define B43_DMA32_RXSTATUS 0x1C
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#define B43_DMA32_RXDPTR 0x00000FFF
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#define B43_DMA32_RXSTATE 0x0000F000
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#define B43_DMA32_RXSTAT_DISABLED 0x00000000
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#define B43_DMA32_RXSTAT_ACTIVE 0x00001000
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#define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000
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#define B43_DMA32_RXSTAT_STOPPED 0x00003000
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#define B43_DMA32_RXERROR 0x000F0000
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#define B43_DMA32_RXERR_NOERR 0x00000000
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#define B43_DMA32_RXERR_PROT 0x00010000
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#define B43_DMA32_RXERR_OVERFLOW 0x00020000
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#define B43_DMA32_RXERR_BUFWRITE 0x00030000
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#define B43_DMA32_RXERR_DESCREAD 0x00040000
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#define B43_DMA32_RXACTIVE 0xFFF00000
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/* 32-bit DMA descriptor. */
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struct b43_dmadesc32 {
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__le32 control;
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__le32 address;
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} __attribute__ ((__packed__));
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#define B43_DMA32_DCTL_BYTECNT 0x00001FFF
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#define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000
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#define B43_DMA32_DCTL_ADDREXT_SHIFT 16
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#define B43_DMA32_DCTL_DTABLEEND 0x10000000
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#define B43_DMA32_DCTL_IRQ 0x20000000
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#define B43_DMA32_DCTL_FRAMEEND 0x40000000
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#define B43_DMA32_DCTL_FRAMESTART 0x80000000
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/*** 64-bit DMA Engine. ***/
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/* 64-bit DMA controller registers. */
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#define B43_DMA64_TXCTL 0x00
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#define B43_DMA64_TXENABLE 0x00000001
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#define B43_DMA64_TXSUSPEND 0x00000002
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#define B43_DMA64_TXLOOPBACK 0x00000004
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#define B43_DMA64_TXFLUSH 0x00000010
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#define B43_DMA64_TXADDREXT_MASK 0x00030000
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#define B43_DMA64_TXADDREXT_SHIFT 16
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#define B43_DMA64_TXINDEX 0x04
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#define B43_DMA64_TXRINGLO 0x08
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#define B43_DMA64_TXRINGHI 0x0C
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#define B43_DMA64_TXSTATUS 0x10
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#define B43_DMA64_TXSTATDPTR 0x00001FFF
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#define B43_DMA64_TXSTAT 0xF0000000
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#define B43_DMA64_TXSTAT_DISABLED 0x00000000
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#define B43_DMA64_TXSTAT_ACTIVE 0x10000000
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#define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000
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#define B43_DMA64_TXSTAT_STOPPED 0x30000000
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#define B43_DMA64_TXSTAT_SUSP 0x40000000
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#define B43_DMA64_TXERROR 0x14
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#define B43_DMA64_TXERRDPTR 0x0001FFFF
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#define B43_DMA64_TXERR 0xF0000000
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#define B43_DMA64_TXERR_NOERR 0x00000000
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#define B43_DMA64_TXERR_PROT 0x10000000
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#define B43_DMA64_TXERR_UNDERRUN 0x20000000
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#define B43_DMA64_TXERR_TRANSFER 0x30000000
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#define B43_DMA64_TXERR_DESCREAD 0x40000000
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#define B43_DMA64_TXERR_CORE 0x50000000
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#define B43_DMA64_RXCTL 0x20
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#define B43_DMA64_RXENABLE 0x00000001
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#define B43_DMA64_RXFROFF_MASK 0x000000FE
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#define B43_DMA64_RXFROFF_SHIFT 1
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#define B43_DMA64_RXDIRECTFIFO 0x00000100
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#define B43_DMA64_RXADDREXT_MASK 0x00030000
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#define B43_DMA64_RXADDREXT_SHIFT 16
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#define B43_DMA64_RXINDEX 0x24
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#define B43_DMA64_RXRINGLO 0x28
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#define B43_DMA64_RXRINGHI 0x2C
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#define B43_DMA64_RXSTATUS 0x30
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#define B43_DMA64_RXSTATDPTR 0x00001FFF
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#define B43_DMA64_RXSTAT 0xF0000000
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#define B43_DMA64_RXSTAT_DISABLED 0x00000000
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#define B43_DMA64_RXSTAT_ACTIVE 0x10000000
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#define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000
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#define B43_DMA64_RXSTAT_STOPPED 0x30000000
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#define B43_DMA64_RXSTAT_SUSP 0x40000000
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#define B43_DMA64_RXERROR 0x34
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#define B43_DMA64_RXERRDPTR 0x0001FFFF
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#define B43_DMA64_RXERR 0xF0000000
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#define B43_DMA64_RXERR_NOERR 0x00000000
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#define B43_DMA64_RXERR_PROT 0x10000000
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#define B43_DMA64_RXERR_UNDERRUN 0x20000000
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#define B43_DMA64_RXERR_TRANSFER 0x30000000
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#define B43_DMA64_RXERR_DESCREAD 0x40000000
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#define B43_DMA64_RXERR_CORE 0x50000000
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/* 64-bit DMA descriptor. */
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struct b43_dmadesc64 {
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__le32 control0;
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__le32 control1;
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__le32 address_low;
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__le32 address_high;
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} __attribute__ ((__packed__));
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#define B43_DMA64_DCTL0_DTABLEEND 0x10000000
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#define B43_DMA64_DCTL0_IRQ 0x20000000
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#define B43_DMA64_DCTL0_FRAMEEND 0x40000000
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#define B43_DMA64_DCTL0_FRAMESTART 0x80000000
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#define B43_DMA64_DCTL1_BYTECNT 0x00001FFF
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#define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000
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#define B43_DMA64_DCTL1_ADDREXT_SHIFT 16
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struct b43_dmadesc_generic {
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union {
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struct b43_dmadesc32 dma32;
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struct b43_dmadesc64 dma64;
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} __attribute__ ((__packed__));
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} __attribute__ ((__packed__));
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/* Misc DMA constants */
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#define B43_DMA0_RX_FRAMEOFFSET 30
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/* DMA engine tuning knobs */
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#define B43_TXRING_SLOTS 256
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#define B43_RXRING_SLOTS 64
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#define B43_DMA0_RX_BUFFERSIZE IEEE80211_MAX_FRAME_LEN
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struct sk_buff;
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struct b43_private;
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struct b43_txstatus;
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struct b43_dmadesc_meta {
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/* The kernel DMA-able buffer. */
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struct sk_buff *skb;
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/* DMA base bus-address of the descriptor buffer. */
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dma_addr_t dmaaddr;
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/* ieee80211 TX status. Only used once per 802.11 frag. */
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bool is_last_fragment;
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};
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struct b43_dmaring;
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/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
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struct b43_dma_ops {
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struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
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int slot,
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struct b43_dmadesc_meta **
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meta);
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void (*fill_descriptor) (struct b43_dmaring * ring,
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struct b43_dmadesc_generic * desc,
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dma_addr_t dmaaddr, u16 bufsize, int start,
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int end, int irq);
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void (*poke_tx) (struct b43_dmaring * ring, int slot);
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void (*tx_suspend) (struct b43_dmaring * ring);
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void (*tx_resume) (struct b43_dmaring * ring);
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int (*get_current_rxslot) (struct b43_dmaring * ring);
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void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
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};
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enum b43_dmatype {
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B43_DMA_30BIT = 30,
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B43_DMA_32BIT = 32,
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B43_DMA_64BIT = 64,
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};
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struct b43_dmaring {
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/* Lowlevel DMA ops. */
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const struct b43_dma_ops *ops;
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/* Kernel virtual base address of the ring memory. */
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void *descbase;
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/* Meta data about all descriptors. */
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struct b43_dmadesc_meta *meta;
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/* Cache of TX headers for each TX frame.
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* This is to avoid an allocation on each TX.
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* This is NULL for an RX ring.
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*/
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u8 *txhdr_cache;
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/* (Unadjusted) DMA base bus-address of the ring memory. */
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dma_addr_t dmabase;
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/* Number of descriptor slots in the ring. */
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int nr_slots;
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/* Number of used descriptor slots. */
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int used_slots;
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/* Currently used slot in the ring. */
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int current_slot;
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/* Total number of packets sent. Statistics only. */
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unsigned int nr_tx_packets;
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/* Frameoffset in octets. */
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u32 frameoffset;
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/* Descriptor buffer size. */
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u16 rx_buffersize;
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/* The MMIO base register of the DMA controller. */
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u16 mmio_base;
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/* DMA controller index number (0-5). */
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int index;
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/* Boolean. Is this a TX ring? */
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bool tx;
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/* The type of DMA engine used. */
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enum b43_dmatype type;
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/* Boolean. Is this ring stopped at ieee80211 level? */
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bool stopped;
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/* The QOS priority assigned to this ring. Only used for TX rings.
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* This is the mac80211 "queue" value. */
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u8 queue_prio;
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/* Pointers and size of the originally allocated and mapped memory
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* region for the descriptor ring. */
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void *alloc_descbase;
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dma_addr_t alloc_dmabase;
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unsigned int alloc_descsize;
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/* Pointer to our wireless device. */
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struct b43_wldev *dev;
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#ifdef CONFIG_B43_DEBUG
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/* Maximum number of used slots. */
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int max_used_slots;
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/* Last time we injected a ring overflow. */
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unsigned long last_injected_overflow;
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/* Statistics: Number of successfully transmitted packets */
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u64 nr_succeed_tx_packets;
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/* Statistics: Number of failed TX packets */
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u64 nr_failed_tx_packets;
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/* Statistics: Total number of TX plus all retries. */
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u64 nr_total_packet_tries;
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#endif /* CONFIG_B43_DEBUG */
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};
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static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
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{
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return b43_read32(ring->dev, ring->mmio_base + offset);
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}
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static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
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{
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b43_write32(ring->dev, ring->mmio_base + offset, value);
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}
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int b43_dma_init(struct b43_wldev *dev);
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void b43_dma_free(struct b43_wldev *dev);
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void b43_dma_tx_suspend(struct b43_wldev *dev);
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void b43_dma_tx_resume(struct b43_wldev *dev);
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void b43_dma_get_tx_stats(struct b43_wldev *dev,
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struct ieee80211_tx_queue_stats *stats);
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int b43_dma_tx(struct b43_wldev *dev,
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struct sk_buff *skb);
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void b43_dma_handle_txstatus(struct b43_wldev *dev,
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const struct b43_txstatus *status);
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void b43_dma_rx(struct b43_dmaring *ring);
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void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
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unsigned int engine_index, bool enable);
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#endif /* B43_DMA_H_ */
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