mirror of
https://github.com/edk2-porting/linux-next.git
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b02038faa7
Move host core initialization and host channel routines into hcd.c. This allows these functions to only be compiled in host-enabled driver configurations (DRD or host-only). Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
1648 lines
45 KiB
C
1648 lines
45 KiB
C
/*
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* core.c - DesignWare HS OTG Controller common routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The Core code provides basic services for accessing and managing the
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* DWC_otg hardware. These services are used by both the Host Controller
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* Driver and the Peripheral Controller Driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ch11.h>
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#include "core.h"
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#include "hcd.h"
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/**
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* dwc2_backup_global_registers() - Backup global controller registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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/* Backup global regs */
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gr = &hsotg->gr_backup;
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gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
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gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
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gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
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gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
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gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
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gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
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gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
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gr->valid = true;
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return 0;
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}
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/**
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* dwc2_restore_global_registers() - Restore controller global registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore global regs */
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gr = &hsotg->gr_backup;
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if (!gr->valid) {
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dev_err(hsotg->dev, "%s: no global registers to restore\n",
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__func__);
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return -EINVAL;
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}
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gr->valid = false;
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dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
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dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
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dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
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dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
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dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
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dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
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dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
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dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
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dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
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return 0;
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}
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/**
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* dwc2_exit_hibernation() - Exit controller from Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @restore: Controller registers need to be restored
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*/
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int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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return -ENOTSUPP;
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_STOPPCLK;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_PWRCLMP;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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udelay(100);
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if (restore) {
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ret = dwc2_restore_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_restore_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_restore_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore device registers\n",
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__func__);
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return ret;
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}
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}
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}
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return ret;
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}
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/**
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* dwc2_enter_hibernation() - Put controller in Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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return -ENOTSUPP;
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/* Backup all registers */
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ret = dwc2_backup_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup global registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_backup_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_backup_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup device registers\n",
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__func__);
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return ret;
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}
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}
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/*
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* Clear any pending interrupts since dwc2 will not be able to
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* clear them after entering hibernation.
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*/
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dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
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/* Put the controller in low power state */
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgcctl |= PCGCTL_PWRCLMP;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_RSTPDWNMODULE;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_STOPPCLK;
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dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
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return ret;
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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int dwc2_core_reset(struct dwc2_hsotg *hsotg)
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{
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u32 greset;
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int count = 0;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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/* Core Soft Reset */
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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greset |= GRSTCTL_CSFTRST;
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dwc2_writel(greset, hsotg->regs + GRSTCTL);
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! Soft Reset GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (greset & GRSTCTL_CSFTRST);
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/* Wait for AHB master IDLE state */
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count = 0;
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! AHB Idle GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (!(greset & GRSTCTL_AHBIDLE));
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return 0;
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}
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/*
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* Force the mode of the controller.
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*
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* Forcing the mode is needed for two cases:
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*
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* 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
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* controller to stay in a particular mode regardless of ID pin
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* changes. We do this usually after a core reset.
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*
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* 2) During probe we want to read reset values of the hw
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* configuration registers that are only available in either host or
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* device mode. We may need to force the mode if the current mode does
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* not allow us to access the register in the mode that we want.
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*
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* In either case it only makes sense to force the mode if the
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* controller hardware is OTG capable.
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*
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* Checks are done in this function to determine whether doing a force
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* would be valid or not.
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*
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* If a force is done, it requires a 25ms delay to take effect.
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*
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* Returns true if the mode was forced.
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*/
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static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
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{
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u32 gusbcfg;
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u32 set;
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u32 clear;
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dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
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/*
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* Force mode has no effect if the hardware is not OTG.
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*/
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if (!dwc2_hw_is_otg(hsotg))
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return false;
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/*
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* If dr_mode is either peripheral or host only, there is no
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* need to ever force the mode to the opposite mode.
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*/
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if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
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return false;
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if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
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return false;
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gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
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clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
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gusbcfg &= ~clear;
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gusbcfg |= set;
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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msleep(25);
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return true;
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}
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/*
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* Clears the force mode bits.
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*/
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static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
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{
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u32 gusbcfg;
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gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
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gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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/*
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* NOTE: This long sleep is _very_ important, otherwise the core will
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* not stay in host mode after a connector ID change!
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*/
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msleep(25);
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}
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/*
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* Sets or clears force mode based on the dr_mode parameter.
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*/
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void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
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{
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switch (hsotg->dr_mode) {
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case USB_DR_MODE_HOST:
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dwc2_force_mode(hsotg, true);
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break;
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case USB_DR_MODE_PERIPHERAL:
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dwc2_force_mode(hsotg, false);
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break;
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case USB_DR_MODE_OTG:
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dwc2_clear_force_mode(hsotg);
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break;
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default:
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dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
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__func__, hsotg->dr_mode);
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break;
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}
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/*
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* NOTE: This is required for some rockchip soc based
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* platforms.
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*/
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msleep(50);
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*
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* Additionally this will apply force mode as per the hsotg->dr_mode
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* parameter.
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*/
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int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
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{
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int retval;
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retval = dwc2_core_reset(hsotg);
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if (retval)
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return retval;
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dwc2_force_dr_mode(hsotg);
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return 0;
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}
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/**
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* dwc2_dump_host_registers() - Prints the host registers
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*
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* @hsotg: Programming view of DWC_otg controller
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*
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* NOTE: This function will be removed once the peripheral controller code
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* is integrated and the driver is stable
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*/
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void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
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{
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#ifdef DEBUG
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u32 __iomem *addr;
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int i;
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dev_dbg(hsotg->dev, "Host Global Registers\n");
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addr = hsotg->regs + HCFG;
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dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HFIR;
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dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HFNUM;
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dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HPTXSTS;
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dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HAINT;
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dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HAINTMSK;
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dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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if (hsotg->core_params->dma_desc_enable > 0) {
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addr = hsotg->regs + HFLBADDR;
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dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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}
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addr = hsotg->regs + HPRT0;
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dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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for (i = 0; i < hsotg->core_params->host_channels; i++) {
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dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
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addr = hsotg->regs + HCCHAR(i);
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dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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addr = hsotg->regs + HCSPLT(i);
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dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCINT(i);
|
|
dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCINTMSK(i);
|
|
dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCTSIZ(i);
|
|
dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HCDMA(i);
|
|
dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
if (hsotg->core_params->dma_desc_enable > 0) {
|
|
addr = hsotg->regs + HCDMAB(i);
|
|
dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_dump_global_registers() - Prints the core global registers
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
|
|
{
|
|
#ifdef DEBUG
|
|
u32 __iomem *addr;
|
|
|
|
dev_dbg(hsotg->dev, "Core Global Registers\n");
|
|
addr = hsotg->regs + GOTGCTL;
|
|
dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GOTGINT;
|
|
dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GAHBCFG;
|
|
dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GUSBCFG;
|
|
dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRSTCTL;
|
|
dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GINTSTS;
|
|
dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GINTMSK;
|
|
dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRXSTSR;
|
|
dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GRXFSIZ;
|
|
dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GNPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GNPTXSTS;
|
|
dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GI2CCTL;
|
|
dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GPVNDCTL;
|
|
dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GGPIO;
|
|
dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GUID;
|
|
dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GSNPSID;
|
|
dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG1;
|
|
dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG2;
|
|
dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG3;
|
|
dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GHWCFG4;
|
|
dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GLPMCFG;
|
|
dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GPWRDN;
|
|
dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + GDFIFOCFG;
|
|
dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
addr = hsotg->regs + HPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
|
|
addr = hsotg->regs + PCGCTL;
|
|
dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(addr));
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_tx_fifo() - Flushes a Tx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
* @num: Tx FIFO to flush
|
|
*/
|
|
void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
|
|
{
|
|
u32 greset;
|
|
int count = 0;
|
|
|
|
dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
|
|
|
|
greset = GRSTCTL_TXFFLSH;
|
|
greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
|
|
dwc2_writel(greset, hsotg->regs + GRSTCTL);
|
|
|
|
do {
|
|
greset = dwc2_readl(hsotg->regs + GRSTCTL);
|
|
if (++count > 10000) {
|
|
dev_warn(hsotg->dev,
|
|
"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
|
|
__func__, greset,
|
|
dwc2_readl(hsotg->regs + GNPTXSTS));
|
|
break;
|
|
}
|
|
udelay(1);
|
|
} while (greset & GRSTCTL_TXFFLSH);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_rx_fifo() - Flushes the Rx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 greset;
|
|
int count = 0;
|
|
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
greset = GRSTCTL_RXFFLSH;
|
|
dwc2_writel(greset, hsotg->regs + GRSTCTL);
|
|
|
|
do {
|
|
greset = dwc2_readl(hsotg->regs + GRSTCTL);
|
|
if (++count > 10000) {
|
|
dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
|
|
__func__, greset);
|
|
break;
|
|
}
|
|
udelay(1);
|
|
} while (greset & GRSTCTL_RXFFLSH);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
|
|
|
|
/* Parameter access functions */
|
|
void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
switch (val) {
|
|
case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
|
|
if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
|
|
valid = 0;
|
|
break;
|
|
case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
|
|
switch (hsotg->hw_params.op_mode) {
|
|
case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
|
|
case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
|
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
|
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
|
|
break;
|
|
default:
|
|
valid = 0;
|
|
break;
|
|
}
|
|
break;
|
|
case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
|
|
/* always valid */
|
|
break;
|
|
default:
|
|
valid = 0;
|
|
break;
|
|
}
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for otg_cap parameter. Check HW configuration.\n",
|
|
val);
|
|
switch (hsotg->hw_params.op_mode) {
|
|
case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
|
|
val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
|
|
break;
|
|
case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
|
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
|
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
|
|
val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
|
|
break;
|
|
default:
|
|
val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
|
|
break;
|
|
}
|
|
dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->otg_cap = val;
|
|
}
|
|
|
|
void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
|
|
valid = 0;
|
|
if (val < 0)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for dma_enable parameter. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
|
|
dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->dma_enable = val;
|
|
}
|
|
|
|
void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
|
|
!hsotg->hw_params.dma_desc_enable))
|
|
valid = 0;
|
|
if (val < 0)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
|
|
val);
|
|
val = (hsotg->core_params->dma_enable > 0 &&
|
|
hsotg->hw_params.dma_desc_enable);
|
|
dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->dma_desc_enable = val;
|
|
}
|
|
|
|
void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
|
|
!hsotg->hw_params.dma_desc_enable))
|
|
valid = 0;
|
|
if (val < 0)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
|
|
val);
|
|
val = (hsotg->core_params->dma_enable > 0 &&
|
|
hsotg->hw_params.dma_desc_enable);
|
|
}
|
|
|
|
hsotg->core_params->dma_desc_fs_enable = val;
|
|
dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
|
|
}
|
|
|
|
void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
|
|
int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"Wrong value for host_support_fs_low_power\n");
|
|
dev_err(hsotg->dev,
|
|
"host_support_fs_low_power must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev,
|
|
"Setting host_support_fs_low_power to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->host_support_fs_ls_low_power = val;
|
|
}
|
|
|
|
void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
|
|
valid = 0;
|
|
if (val < 0)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.enable_dynamic_fifo;
|
|
dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->enable_dynamic_fifo = val;
|
|
}
|
|
|
|
void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for host_rx_fifo_size. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.host_rx_fifo_size;
|
|
dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->host_rx_fifo_size = val;
|
|
}
|
|
|
|
void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.host_nperio_tx_fifo_size;
|
|
dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
|
|
val);
|
|
}
|
|
|
|
hsotg->core_params->host_nperio_tx_fifo_size = val;
|
|
}
|
|
|
|
void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.host_perio_tx_fifo_size;
|
|
dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
|
|
val);
|
|
}
|
|
|
|
hsotg->core_params->host_perio_tx_fifo_size = val;
|
|
}
|
|
|
|
void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for max_transfer_size. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.max_transfer_size;
|
|
dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->max_transfer_size = val;
|
|
}
|
|
|
|
void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 15 || val > hsotg->hw_params.max_packet_count)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for max_packet_count. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.max_packet_count;
|
|
dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->max_packet_count = val;
|
|
}
|
|
|
|
void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (val < 1 || val > hsotg->hw_params.host_channels)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for host_channels. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.host_channels;
|
|
dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->host_channels = val;
|
|
}
|
|
|
|
void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 0;
|
|
u32 hs_phy_type, fs_phy_type;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
|
|
DWC2_PHY_TYPE_PARAM_ULPI)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for phy_type\n");
|
|
dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
|
|
}
|
|
|
|
valid = 0;
|
|
}
|
|
|
|
hs_phy_type = hsotg->hw_params.hs_phy_type;
|
|
fs_phy_type = hsotg->hw_params.fs_phy_type;
|
|
if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
|
|
(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
|
|
hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
|
|
valid = 1;
|
|
else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
|
|
(hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
|
|
hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
|
|
valid = 1;
|
|
else if (val == DWC2_PHY_TYPE_PARAM_FS &&
|
|
fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
|
|
valid = 1;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for phy_type. Check HW configuration.\n",
|
|
val);
|
|
val = DWC2_PHY_TYPE_PARAM_FS;
|
|
if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
|
|
if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
|
|
hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
|
|
val = DWC2_PHY_TYPE_PARAM_UTMI;
|
|
else
|
|
val = DWC2_PHY_TYPE_PARAM_ULPI;
|
|
}
|
|
dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->phy_type = val;
|
|
}
|
|
|
|
static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
|
|
{
|
|
return hsotg->core_params->phy_type;
|
|
}
|
|
|
|
void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for speed parameter\n");
|
|
dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
|
|
}
|
|
valid = 0;
|
|
}
|
|
|
|
if (val == DWC2_SPEED_PARAM_HIGH &&
|
|
dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for speed parameter. Check HW configuration.\n",
|
|
val);
|
|
val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
|
|
DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
|
|
dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->speed = val;
|
|
}
|
|
|
|
void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
|
|
DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"Wrong value for host_ls_low_power_phy_clk parameter\n");
|
|
dev_err(hsotg->dev,
|
|
"host_ls_low_power_phy_clk must be 0 or 1\n");
|
|
}
|
|
valid = 0;
|
|
}
|
|
|
|
if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
|
|
dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
|
|
val);
|
|
val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
|
|
? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
|
|
: DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
|
|
dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
|
|
val);
|
|
}
|
|
|
|
hsotg->core_params->host_ls_low_power_phy_clk = val;
|
|
}
|
|
|
|
void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
|
|
dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->phy_ulpi_ddr = val;
|
|
}
|
|
|
|
void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"Wrong value for phy_ulpi_ext_vbus\n");
|
|
dev_err(hsotg->dev,
|
|
"phy_ulpi_ext_vbus must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->phy_ulpi_ext_vbus = val;
|
|
}
|
|
|
|
void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 0;
|
|
|
|
switch (hsotg->hw_params.utmi_phy_data_width) {
|
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
|
|
valid = (val == 8);
|
|
break;
|
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
|
|
valid = (val == 16);
|
|
break;
|
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
|
|
valid = (val == 8 || val == 16);
|
|
break;
|
|
}
|
|
|
|
if (!valid) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for phy_utmi_width. Check HW configuration.\n",
|
|
val);
|
|
}
|
|
val = (hsotg->hw_params.utmi_phy_data_width ==
|
|
GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
|
|
dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->phy_utmi_width = val;
|
|
}
|
|
|
|
void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
|
|
dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->ulpi_fs_ls = val;
|
|
}
|
|
|
|
void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for ts_dline\n");
|
|
dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->ts_dline = val;
|
|
}
|
|
|
|
void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
|
|
dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
|
|
}
|
|
|
|
valid = 0;
|
|
}
|
|
|
|
if (val == 1 && !(hsotg->hw_params.i2c_enable))
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for i2c_enable. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.i2c_enable;
|
|
dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->i2c_enable = val;
|
|
}
|
|
|
|
void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"Wrong value for en_multiple_tx_fifo,\n");
|
|
dev_err(hsotg->dev,
|
|
"en_multiple_tx_fifo must be 0 or 1\n");
|
|
}
|
|
valid = 0;
|
|
}
|
|
|
|
if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.en_multiple_tx_fifo;
|
|
dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->en_multiple_tx_fifo = val;
|
|
}
|
|
|
|
void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
int valid = 1;
|
|
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"'%d' invalid for parameter reload_ctl\n", val);
|
|
dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
|
|
}
|
|
valid = 0;
|
|
}
|
|
|
|
if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
|
|
valid = 0;
|
|
|
|
if (!valid) {
|
|
if (val >= 0)
|
|
dev_err(hsotg->dev,
|
|
"%d invalid for parameter reload_ctl. Check HW configuration.\n",
|
|
val);
|
|
val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
|
|
dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->reload_ctl = val;
|
|
}
|
|
|
|
void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (val != -1)
|
|
hsotg->core_params->ahbcfg = val;
|
|
else
|
|
hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
|
|
GAHBCFG_HBSTLEN_SHIFT;
|
|
}
|
|
|
|
void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"'%d' invalid for parameter otg_ver\n", val);
|
|
dev_err(hsotg->dev,
|
|
"otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->otg_ver = val;
|
|
}
|
|
|
|
static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"'%d' invalid for parameter uframe_sched\n",
|
|
val);
|
|
dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
|
|
}
|
|
val = 1;
|
|
dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->uframe_sched = val;
|
|
}
|
|
|
|
static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
|
|
int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"'%d' invalid for parameter external_id_pin_ctl\n",
|
|
val);
|
|
dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->external_id_pin_ctl = val;
|
|
}
|
|
|
|
static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
|
|
int val)
|
|
{
|
|
if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
|
|
if (val >= 0) {
|
|
dev_err(hsotg->dev,
|
|
"'%d' invalid for parameter hibernation\n",
|
|
val);
|
|
dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
|
|
}
|
|
val = 0;
|
|
dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
|
|
}
|
|
|
|
hsotg->core_params->hibernation = val;
|
|
}
|
|
|
|
/*
|
|
* This function is called during module intialization to pass module parameters
|
|
* for the DWC_otg core.
|
|
*/
|
|
void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
|
|
const struct dwc2_core_params *params)
|
|
{
|
|
dev_dbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
dwc2_set_param_otg_cap(hsotg, params->otg_cap);
|
|
dwc2_set_param_dma_enable(hsotg, params->dma_enable);
|
|
dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
|
|
dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
|
|
dwc2_set_param_host_support_fs_ls_low_power(hsotg,
|
|
params->host_support_fs_ls_low_power);
|
|
dwc2_set_param_enable_dynamic_fifo(hsotg,
|
|
params->enable_dynamic_fifo);
|
|
dwc2_set_param_host_rx_fifo_size(hsotg,
|
|
params->host_rx_fifo_size);
|
|
dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
|
|
params->host_nperio_tx_fifo_size);
|
|
dwc2_set_param_host_perio_tx_fifo_size(hsotg,
|
|
params->host_perio_tx_fifo_size);
|
|
dwc2_set_param_max_transfer_size(hsotg,
|
|
params->max_transfer_size);
|
|
dwc2_set_param_max_packet_count(hsotg,
|
|
params->max_packet_count);
|
|
dwc2_set_param_host_channels(hsotg, params->host_channels);
|
|
dwc2_set_param_phy_type(hsotg, params->phy_type);
|
|
dwc2_set_param_speed(hsotg, params->speed);
|
|
dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
|
|
params->host_ls_low_power_phy_clk);
|
|
dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
|
|
dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
|
|
params->phy_ulpi_ext_vbus);
|
|
dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
|
|
dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
|
|
dwc2_set_param_ts_dline(hsotg, params->ts_dline);
|
|
dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
|
|
dwc2_set_param_en_multiple_tx_fifo(hsotg,
|
|
params->en_multiple_tx_fifo);
|
|
dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
|
|
dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
|
|
dwc2_set_param_otg_ver(hsotg, params->otg_ver);
|
|
dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
|
|
dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
|
|
dwc2_set_param_hibernation(hsotg, params->hibernation);
|
|
}
|
|
|
|
/*
|
|
* Forces either host or device mode if the controller is not
|
|
* currently in that mode.
|
|
*
|
|
* Returns true if the mode was forced.
|
|
*/
|
|
static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
|
|
{
|
|
if (host && dwc2_is_host_mode(hsotg))
|
|
return false;
|
|
else if (!host && dwc2_is_device_mode(hsotg))
|
|
return false;
|
|
|
|
return dwc2_force_mode(hsotg, host);
|
|
}
|
|
|
|
/*
|
|
* Gets host hardware parameters. Forces host mode if not currently in
|
|
* host mode. Should be called immediately after a core soft reset in
|
|
* order to get the reset values.
|
|
*/
|
|
static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
|
|
{
|
|
struct dwc2_hw_params *hw = &hsotg->hw_params;
|
|
u32 gnptxfsiz;
|
|
u32 hptxfsiz;
|
|
bool forced;
|
|
|
|
if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
|
|
return;
|
|
|
|
forced = dwc2_force_mode_if_needed(hsotg, true);
|
|
|
|
gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
|
|
hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
|
|
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
|
|
dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
|
|
|
|
if (forced)
|
|
dwc2_clear_force_mode(hsotg);
|
|
|
|
hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
|
|
FIFOSIZE_DEPTH_SHIFT;
|
|
hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
|
|
FIFOSIZE_DEPTH_SHIFT;
|
|
}
|
|
|
|
/*
|
|
* Gets device hardware parameters. Forces device mode if not
|
|
* currently in device mode. Should be called immediately after a core
|
|
* soft reset in order to get the reset values.
|
|
*/
|
|
static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
|
|
{
|
|
struct dwc2_hw_params *hw = &hsotg->hw_params;
|
|
bool forced;
|
|
u32 gnptxfsiz;
|
|
|
|
if (hsotg->dr_mode == USB_DR_MODE_HOST)
|
|
return;
|
|
|
|
forced = dwc2_force_mode_if_needed(hsotg, false);
|
|
|
|
gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
|
|
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
|
|
|
|
if (forced)
|
|
dwc2_clear_force_mode(hsotg);
|
|
|
|
hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
|
|
FIFOSIZE_DEPTH_SHIFT;
|
|
}
|
|
|
|
/**
|
|
* During device initialization, read various hardware configuration
|
|
* registers and interpret the contents.
|
|
*/
|
|
int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
|
|
{
|
|
struct dwc2_hw_params *hw = &hsotg->hw_params;
|
|
unsigned width;
|
|
u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
|
|
u32 grxfsiz;
|
|
|
|
/*
|
|
* Attempt to ensure this device is really a DWC_otg Controller.
|
|
* Read and verify the GSNPSID register contents. The value should be
|
|
* 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
|
|
* as in "OTG version 2.xx" or "OTG version 3.xx".
|
|
*/
|
|
hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
|
|
if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
|
|
(hw->snpsid & 0xfffff000) != 0x4f543000) {
|
|
dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
|
|
hw->snpsid);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
|
|
hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
|
|
hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
|
|
|
|
hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
|
|
hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
|
|
hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
|
|
hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
|
|
grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
|
|
|
|
dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
|
|
dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
|
|
dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
|
|
dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
|
|
dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
|
|
|
|
/*
|
|
* Host specific hardware parameters. Reading these parameters
|
|
* requires the controller to be in host mode. The mode will
|
|
* be forced, if necessary, to read these values.
|
|
*/
|
|
dwc2_get_host_hwparams(hsotg);
|
|
dwc2_get_dev_hwparams(hsotg);
|
|
|
|
/* hwcfg1 */
|
|
hw->dev_ep_dirs = hwcfg1;
|
|
|
|
/* hwcfg2 */
|
|
hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
|
|
GHWCFG2_OP_MODE_SHIFT;
|
|
hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
|
|
GHWCFG2_ARCHITECTURE_SHIFT;
|
|
hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
|
|
hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
|
|
GHWCFG2_NUM_HOST_CHAN_SHIFT);
|
|
hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
|
|
GHWCFG2_HS_PHY_TYPE_SHIFT;
|
|
hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
|
|
GHWCFG2_FS_PHY_TYPE_SHIFT;
|
|
hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
|
|
GHWCFG2_NUM_DEV_EP_SHIFT;
|
|
hw->nperio_tx_q_depth =
|
|
(hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
|
|
GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
|
|
hw->host_perio_tx_q_depth =
|
|
(hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
|
|
GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
|
|
hw->dev_token_q_depth =
|
|
(hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
|
|
GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
|
|
|
|
/* hwcfg3 */
|
|
width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
|
|
GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
|
|
hw->max_transfer_size = (1 << (width + 11)) - 1;
|
|
width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
|
|
GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
|
|
hw->max_packet_count = (1 << (width + 4)) - 1;
|
|
hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
|
|
hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
|
|
GHWCFG3_DFIFO_DEPTH_SHIFT;
|
|
|
|
/* hwcfg4 */
|
|
hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
|
|
hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
|
|
GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
|
|
hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
|
|
hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
|
|
hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
|
|
GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
|
|
|
|
/* fifo sizes */
|
|
hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
|
|
GRXFSIZ_DEPTH_SHIFT;
|
|
|
|
dev_dbg(hsotg->dev, "Detected values from hardware:\n");
|
|
dev_dbg(hsotg->dev, " op_mode=%d\n",
|
|
hw->op_mode);
|
|
dev_dbg(hsotg->dev, " arch=%d\n",
|
|
hw->arch);
|
|
dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
|
|
hw->dma_desc_enable);
|
|
dev_dbg(hsotg->dev, " power_optimized=%d\n",
|
|
hw->power_optimized);
|
|
dev_dbg(hsotg->dev, " i2c_enable=%d\n",
|
|
hw->i2c_enable);
|
|
dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
|
|
hw->hs_phy_type);
|
|
dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
|
|
hw->fs_phy_type);
|
|
dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
|
|
hw->utmi_phy_data_width);
|
|
dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
|
|
hw->num_dev_ep);
|
|
dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
|
|
hw->num_dev_perio_in_ep);
|
|
dev_dbg(hsotg->dev, " host_channels=%d\n",
|
|
hw->host_channels);
|
|
dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
|
|
hw->max_transfer_size);
|
|
dev_dbg(hsotg->dev, " max_packet_count=%d\n",
|
|
hw->max_packet_count);
|
|
dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
|
|
hw->nperio_tx_q_depth);
|
|
dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
|
|
hw->host_perio_tx_q_depth);
|
|
dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
|
|
hw->dev_token_q_depth);
|
|
dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
|
|
hw->enable_dynamic_fifo);
|
|
dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
|
|
hw->en_multiple_tx_fifo);
|
|
dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
|
|
hw->total_fifo_size);
|
|
dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
|
|
hw->host_rx_fifo_size);
|
|
dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
|
|
hw->host_nperio_tx_fifo_size);
|
|
dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
|
|
hw->host_perio_tx_fifo_size);
|
|
dev_dbg(hsotg->dev, "\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Sets all parameters to the given value.
|
|
*
|
|
* Assumes that the dwc2_core_params struct contains only integers.
|
|
*/
|
|
void dwc2_set_all_params(struct dwc2_core_params *params, int value)
|
|
{
|
|
int *p = (int *)params;
|
|
size_t size = sizeof(*params) / sizeof(*p);
|
|
int i;
|
|
|
|
for (i = 0; i < size; i++)
|
|
p[i] = value;
|
|
}
|
|
|
|
|
|
u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
|
|
{
|
|
return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
|
|
}
|
|
|
|
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
|
|
{
|
|
if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
|
|
return false;
|
|
else
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* dwc2_enable_global_interrupts() - Enables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
|
|
|
|
ahbcfg |= GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
|
|
}
|
|
|
|
/**
|
|
* dwc2_disable_global_interrupts() - Disables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
|
|
|
|
ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
|
|
}
|
|
|
|
/* Returns the controller's GHWCFG2.OTG_MODE. */
|
|
unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
|
|
|
|
return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
|
|
GHWCFG2_OP_MODE_SHIFT;
|
|
}
|
|
|
|
/* Returns true if the controller is capable of DRD. */
|
|
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
|
|
}
|
|
|
|
/* Returns true if the controller is host-only. */
|
|
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
|
|
}
|
|
|
|
/* Returns true if the controller is device-only. */
|
|
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
|
|
MODULE_AUTHOR("Synopsys, Inc.");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|