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5db3ae8b33
Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Silence NULL pointer sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
163 lines
4.9 KiB
C
163 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H
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#define _DT_BINDINGS_CLK_MSM_MMCC_660_H
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#define AHB_CLK_SRC 0
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#define BYTE0_CLK_SRC 1
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#define BYTE1_CLK_SRC 2
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#define CAMSS_GP0_CLK_SRC 3
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#define CAMSS_GP1_CLK_SRC 4
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#define CCI_CLK_SRC 5
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#define CPP_CLK_SRC 6
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#define CSI0_CLK_SRC 7
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#define CSI0PHYTIMER_CLK_SRC 8
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#define CSI1_CLK_SRC 9
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#define CSI1PHYTIMER_CLK_SRC 10
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#define CSI2_CLK_SRC 11
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#define CSI2PHYTIMER_CLK_SRC 12
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#define CSI3_CLK_SRC 13
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#define CSIPHY_CLK_SRC 14
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#define DP_AUX_CLK_SRC 15
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#define DP_CRYPTO_CLK_SRC 16
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#define DP_GTC_CLK_SRC 17
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#define DP_LINK_CLK_SRC 18
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#define DP_PIXEL_CLK_SRC 19
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#define ESC0_CLK_SRC 20
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#define ESC1_CLK_SRC 21
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#define JPEG0_CLK_SRC 22
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#define MCLK0_CLK_SRC 23
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#define MCLK1_CLK_SRC 24
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#define MCLK2_CLK_SRC 25
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#define MCLK3_CLK_SRC 26
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#define MDP_CLK_SRC 27
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#define MMPLL0_PLL 28
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#define MMPLL10_PLL 29
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#define MMPLL1_PLL 30
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#define MMPLL3_PLL 31
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#define MMPLL4_PLL 32
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#define MMPLL5_PLL 33
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#define MMPLL6_PLL 34
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#define MMPLL7_PLL 35
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#define MMPLL8_PLL 36
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#define BIMC_SMMU_AHB_CLK 37
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#define BIMC_SMMU_AXI_CLK 38
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#define CAMSS_AHB_CLK 39
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#define CAMSS_CCI_AHB_CLK 40
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#define CAMSS_CCI_CLK 41
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#define CAMSS_CPHY_CSID0_CLK 42
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#define CAMSS_CPHY_CSID1_CLK 43
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#define CAMSS_CPHY_CSID2_CLK 44
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#define CAMSS_CPHY_CSID3_CLK 45
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#define CAMSS_CPP_AHB_CLK 46
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#define CAMSS_CPP_AXI_CLK 47
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#define CAMSS_CPP_CLK 48
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#define CAMSS_CPP_VBIF_AHB_CLK 49
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#define CAMSS_CSI0_AHB_CLK 50
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#define CAMSS_CSI0_CLK 51
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#define CAMSS_CSI0PHYTIMER_CLK 52
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#define CAMSS_CSI0PIX_CLK 53
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#define CAMSS_CSI0RDI_CLK 54
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#define CAMSS_CSI1_AHB_CLK 55
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#define CAMSS_CSI1_CLK 56
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#define CAMSS_CSI1PHYTIMER_CLK 57
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#define CAMSS_CSI1PIX_CLK 58
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#define CAMSS_CSI1RDI_CLK 59
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#define CAMSS_CSI2_AHB_CLK 60
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#define CAMSS_CSI2_CLK 61
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#define CAMSS_CSI2PHYTIMER_CLK 62
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#define CAMSS_CSI2PIX_CLK 63
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#define CAMSS_CSI2RDI_CLK 64
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#define CAMSS_CSI3_AHB_CLK 65
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#define CAMSS_CSI3_CLK 66
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#define CAMSS_CSI3PIX_CLK 67
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#define CAMSS_CSI3RDI_CLK 68
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#define CAMSS_CSI_VFE0_CLK 69
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#define CAMSS_CSI_VFE1_CLK 70
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#define CAMSS_CSIPHY0_CLK 71
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#define CAMSS_CSIPHY1_CLK 72
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#define CAMSS_CSIPHY2_CLK 73
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#define CAMSS_GP0_CLK 74
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#define CAMSS_GP1_CLK 75
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#define CAMSS_ISPIF_AHB_CLK 76
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#define CAMSS_JPEG0_CLK 77
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#define CAMSS_JPEG_AHB_CLK 78
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#define CAMSS_JPEG_AXI_CLK 79
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#define CAMSS_MCLK0_CLK 80
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#define CAMSS_MCLK1_CLK 81
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#define CAMSS_MCLK2_CLK 82
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#define CAMSS_MCLK3_CLK 83
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#define CAMSS_MICRO_AHB_CLK 84
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#define CAMSS_TOP_AHB_CLK 85
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#define CAMSS_VFE0_AHB_CLK 86
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#define CAMSS_VFE0_CLK 87
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#define CAMSS_VFE0_STREAM_CLK 88
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#define CAMSS_VFE1_AHB_CLK 89
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#define CAMSS_VFE1_CLK 90
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#define CAMSS_VFE1_STREAM_CLK 91
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#define CAMSS_VFE_VBIF_AHB_CLK 92
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#define CAMSS_VFE_VBIF_AXI_CLK 93
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#define CSIPHY_AHB2CRIF_CLK 94
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#define CXO_CLK 95
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#define MDSS_AHB_CLK 96
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#define MDSS_AXI_CLK 97
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#define MDSS_BYTE0_CLK 98
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#define MDSS_BYTE0_INTF_CLK 99
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#define MDSS_BYTE0_INTF_DIV_CLK 100
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#define MDSS_BYTE1_CLK 101
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#define MDSS_BYTE1_INTF_CLK 102
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#define MDSS_DP_AUX_CLK 103
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#define MDSS_DP_CRYPTO_CLK 104
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#define MDSS_DP_GTC_CLK 105
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#define MDSS_DP_LINK_CLK 106
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#define MDSS_DP_LINK_INTF_CLK 107
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#define MDSS_DP_PIXEL_CLK 108
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#define MDSS_ESC0_CLK 109
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#define MDSS_ESC1_CLK 110
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#define MDSS_HDMI_DP_AHB_CLK 111
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#define MDSS_MDP_CLK 112
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#define MDSS_PCLK0_CLK 113
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#define MDSS_PCLK1_CLK 114
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#define MDSS_ROT_CLK 115
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#define MDSS_VSYNC_CLK 116
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#define MISC_AHB_CLK 117
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#define MISC_CXO_CLK 118
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#define MNOC_AHB_CLK 119
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#define SNOC_DVM_AXI_CLK 120
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#define THROTTLE_CAMSS_AHB_CLK 121
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#define THROTTLE_CAMSS_AXI_CLK 122
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#define THROTTLE_MDSS_AHB_CLK 123
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#define THROTTLE_MDSS_AXI_CLK 124
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#define THROTTLE_VIDEO_AHB_CLK 125
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#define THROTTLE_VIDEO_AXI_CLK 126
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#define VIDEO_AHB_CLK 127
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#define VIDEO_AXI_CLK 128
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#define VIDEO_CORE_CLK 129
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#define VIDEO_SUBCORE0_CLK 130
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#define PCLK0_CLK_SRC 131
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#define PCLK1_CLK_SRC 132
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#define ROT_CLK_SRC 133
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#define VFE0_CLK_SRC 134
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#define VFE1_CLK_SRC 135
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#define VIDEO_CORE_CLK_SRC 136
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#define VSYNC_CLK_SRC 137
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#define MDSS_BYTE1_INTF_DIV_CLK 138
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#define AXI_CLK_SRC 139
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#define VENUS_GDSC 0
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#define VENUS_CORE0_GDSC 1
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#define MDSS_GDSC 2
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#define CAMSS_TOP_GDSC 3
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#define CAMSS_VFE0_GDSC 4
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#define CAMSS_VFE1_GDSC 5
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#define CAMSS_CPP_GDSC 6
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#define BIMC_SMMU_GDSC 7
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#define CAMSS_MICRO_BCR 0
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#endif
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