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bdf7805b8c
Add GDSC instances in SDX55 GCC block. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-6-manivannan.sadhasivam@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
118 lines
3.9 KiB
C
118 lines
3.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H
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#define GPLL0 3
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#define GPLL0_OUT_EVEN 4
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#define GPLL4 5
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#define GPLL4_OUT_EVEN 6
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#define GPLL5 7
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#define GCC_AHB_PCIE_LINK_CLK 8
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#define GCC_BLSP1_AHB_CLK 9
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25
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#define GCC_BLSP1_UART1_APPS_CLK 26
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#define GCC_BLSP1_UART1_APPS_CLK_SRC 27
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#define GCC_BLSP1_UART2_APPS_CLK 28
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#define GCC_BLSP1_UART2_APPS_CLK_SRC 29
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#define GCC_BLSP1_UART3_APPS_CLK 30
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#define GCC_BLSP1_UART3_APPS_CLK_SRC 31
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#define GCC_BLSP1_UART4_APPS_CLK 32
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#define GCC_BLSP1_UART4_APPS_CLK_SRC 33
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#define GCC_BOOT_ROM_AHB_CLK 34
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#define GCC_CE1_AHB_CLK 35
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#define GCC_CE1_AXI_CLK 36
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#define GCC_CE1_CLK 37
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#define GCC_CPUSS_AHB_CLK 38
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#define GCC_CPUSS_AHB_CLK_SRC 39
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#define GCC_CPUSS_GNOC_CLK 40
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#define GCC_CPUSS_RBCPR_CLK 41
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#define GCC_CPUSS_RBCPR_CLK_SRC 42
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#define GCC_EMAC_CLK_SRC 43
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#define GCC_EMAC_PTP_CLK_SRC 44
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#define GCC_ETH_AXI_CLK 45
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#define GCC_ETH_PTP_CLK 46
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#define GCC_ETH_RGMII_CLK 47
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#define GCC_ETH_SLAVE_AHB_CLK 48
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#define GCC_GP1_CLK 49
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#define GCC_GP1_CLK_SRC 50
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#define GCC_GP2_CLK 51
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#define GCC_GP2_CLK_SRC 52
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#define GCC_GP3_CLK 53
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#define GCC_GP3_CLK_SRC 54
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#define GCC_PCIE_0_CLKREF_CLK 55
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#define GCC_PCIE_AUX_CLK 56
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#define GCC_PCIE_AUX_PHY_CLK_SRC 57
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#define GCC_PCIE_CFG_AHB_CLK 58
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#define GCC_PCIE_MSTR_AXI_CLK 59
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#define GCC_PCIE_PIPE_CLK 60
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#define GCC_PCIE_RCHNG_PHY_CLK 61
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#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62
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#define GCC_PCIE_SLEEP_CLK 63
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#define GCC_PCIE_SLV_AXI_CLK 64
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#define GCC_PCIE_SLV_Q2A_AXI_CLK 65
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#define GCC_PDM2_CLK 66
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#define GCC_PDM2_CLK_SRC 67
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#define GCC_PDM_AHB_CLK 68
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#define GCC_PDM_XO4_CLK 69
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#define GCC_SDCC1_AHB_CLK 70
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#define GCC_SDCC1_APPS_CLK 71
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#define GCC_SDCC1_APPS_CLK_SRC 72
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 73
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#define GCC_USB30_MASTER_CLK 74
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#define GCC_USB30_MASTER_CLK_SRC 75
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#define GCC_USB30_MOCK_UTMI_CLK 76
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#define GCC_USB30_MOCK_UTMI_CLK_SRC 77
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#define GCC_USB30_MSTR_AXI_CLK 78
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#define GCC_USB30_SLEEP_CLK 79
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#define GCC_USB30_SLV_AHB_CLK 80
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#define GCC_USB3_PHY_AUX_CLK 81
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#define GCC_USB3_PHY_AUX_CLK_SRC 82
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#define GCC_USB3_PHY_PIPE_CLK 83
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#define GCC_USB3_PRIM_CLKREF_CLK 84
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85
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#define GCC_XO_DIV4_CLK 86
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#define GCC_XO_PCIE_LINK_CLK 87
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#define GCC_EMAC_BCR 0
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#define GCC_PCIE_BCR 1
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#define GCC_PCIE_LINK_DOWN_BCR 2
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#define GCC_PCIE_NOCSR_COM_PHY_BCR 3
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#define GCC_PCIE_PHY_BCR 4
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#define GCC_PCIE_PHY_CFG_AHB_BCR 5
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#define GCC_PCIE_PHY_COM_BCR 6
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7
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#define GCC_PDM_BCR 8
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#define GCC_QUSB2PHY_BCR 9
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#define GCC_TCSR_PCIE_BCR 10
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#define GCC_USB30_BCR 11
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#define GCC_USB3_PHY_BCR 12
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#define GCC_USB3PHY_PHY_BCR 13
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14
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/* GCC power domains */
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#define USB30_GDSC 0
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#define PCIE_GDSC 1
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#define EMAC_GDSC 2
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#endif
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