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b538304da7
This will be required in order to support the
modem upstream.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200726111215.22361-2-konradybcio@gmail.com
Fixes: f2a76a2955 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
158 lines
5.1 KiB
C
158 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018, Craig Tatlor.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
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#define _DT_BINDINGS_CLK_MSM_GCC_660_H
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
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#define BLSP1_UART1_APPS_CLK_SRC 8
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#define BLSP1_UART2_APPS_CLK_SRC 9
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
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#define BLSP2_UART1_APPS_CLK_SRC 18
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#define BLSP2_UART2_APPS_CLK_SRC 19
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#define GCC_AGGRE2_UFS_AXI_CLK 20
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#define GCC_AGGRE2_USB3_AXI_CLK 21
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#define GCC_BIMC_GFX_CLK 22
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#define GCC_BIMC_HMSS_AXI_CLK 23
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#define GCC_BIMC_MSS_Q6_AXI_CLK 24
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#define GCC_BLSP1_AHB_CLK 25
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
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#define GCC_BLSP1_UART1_APPS_CLK 34
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#define GCC_BLSP1_UART2_APPS_CLK 35
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#define GCC_BLSP2_AHB_CLK 36
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
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#define GCC_BLSP2_UART1_APPS_CLK 45
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#define GCC_BLSP2_UART2_APPS_CLK 46
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#define GCC_BOOT_ROM_AHB_CLK 47
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#define GCC_CFG_NOC_USB2_AXI_CLK 48
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#define GCC_CFG_NOC_USB3_AXI_CLK 49
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#define GCC_DCC_AHB_CLK 50
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#define GCC_GP1_CLK 51
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#define GCC_GP2_CLK 52
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#define GCC_GP3_CLK 53
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#define GCC_GPU_BIMC_GFX_CLK 54
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#define GCC_GPU_CFG_AHB_CLK 55
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#define GCC_GPU_GPLL0_CLK 56
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#define GCC_GPU_GPLL0_DIV_CLK 57
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#define GCC_HMSS_DVM_BUS_CLK 58
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#define GCC_HMSS_RBCPR_CLK 59
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#define GCC_MMSS_GPLL0_CLK 60
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#define GCC_MMSS_GPLL0_DIV_CLK 61
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#define GCC_MMSS_NOC_CFG_AHB_CLK 62
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#define GCC_MMSS_SYS_NOC_AXI_CLK 63
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#define GCC_MSS_CFG_AHB_CLK 64
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#define GCC_MSS_GPLL0_DIV_CLK 65
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#define GCC_MSS_MNOC_BIMC_AXI_CLK 66
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#define GCC_MSS_Q6_BIMC_AXI_CLK 67
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#define GCC_MSS_SNOC_AXI_CLK 68
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#define GCC_PDM2_CLK 69
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#define GCC_PDM_AHB_CLK 70
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#define GCC_PRNG_AHB_CLK 71
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#define GCC_QSPI_AHB_CLK 72
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#define GCC_QSPI_SER_CLK 73
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#define GCC_SDCC1_AHB_CLK 74
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#define GCC_SDCC1_APPS_CLK 75
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#define GCC_SDCC1_ICE_CORE_CLK 76
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#define GCC_SDCC2_AHB_CLK 77
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#define GCC_SDCC2_APPS_CLK 78
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#define GCC_UFS_AHB_CLK 79
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#define GCC_UFS_AXI_CLK 80
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#define GCC_UFS_CLKREF_CLK 81
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#define GCC_UFS_ICE_CORE_CLK 82
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#define GCC_UFS_PHY_AUX_CLK 83
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#define GCC_UFS_RX_SYMBOL_0_CLK 84
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#define GCC_UFS_RX_SYMBOL_1_CLK 85
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#define GCC_UFS_TX_SYMBOL_0_CLK 86
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#define GCC_UFS_UNIPRO_CORE_CLK 87
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#define GCC_USB20_MASTER_CLK 88
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#define GCC_USB20_MOCK_UTMI_CLK 89
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#define GCC_USB20_SLEEP_CLK 90
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#define GCC_USB30_MASTER_CLK 91
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#define GCC_USB30_MOCK_UTMI_CLK 92
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#define GCC_USB30_SLEEP_CLK 93
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#define GCC_USB3_CLKREF_CLK 94
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#define GCC_USB3_PHY_AUX_CLK 95
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#define GCC_USB3_PHY_PIPE_CLK 96
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
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#define GP1_CLK_SRC 98
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#define GP2_CLK_SRC 99
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#define GP3_CLK_SRC 100
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#define GPLL0 101
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#define GPLL0_EARLY 102
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#define GPLL1 103
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#define GPLL1_EARLY 104
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#define GPLL4 105
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#define GPLL4_EARLY 106
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#define HMSS_GPLL0_CLK_SRC 107
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#define HMSS_GPLL4_CLK_SRC 108
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#define HMSS_RBCPR_CLK_SRC 109
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#define PDM2_CLK_SRC 110
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#define QSPI_SER_CLK_SRC 111
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#define SDCC1_APPS_CLK_SRC 112
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#define SDCC1_ICE_CORE_CLK_SRC 113
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#define SDCC2_APPS_CLK_SRC 114
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#define UFS_AXI_CLK_SRC 115
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#define UFS_ICE_CORE_CLK_SRC 116
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#define UFS_PHY_AUX_CLK_SRC 117
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#define UFS_UNIPRO_CORE_CLK_SRC 118
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#define USB20_MASTER_CLK_SRC 119
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#define USB20_MOCK_UTMI_CLK_SRC 120
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#define USB30_MASTER_CLK_SRC 121
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#define USB30_MOCK_UTMI_CLK_SRC 122
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#define USB3_PHY_AUX_CLK_SRC 123
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#define GPLL0_OUT_MSSCC 124
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#define GCC_UFS_AXI_HW_CTL_CLK 125
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#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
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#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
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#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
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#define GCC_RX0_USB2_CLKREF_CLK 129
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#define GCC_RX1_USB2_CLKREF_CLK 130
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#define PCIE_0_GDSC 0
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#define UFS_GDSC 1
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#define USB_30_GDSC 2
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#define GCC_QUSB2PHY_PRIM_BCR 0
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#define GCC_QUSB2PHY_SEC_BCR 1
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#define GCC_UFS_BCR 2
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#define GCC_USB3_DP_PHY_BCR 3
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#define GCC_USB3_PHY_BCR 4
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#define GCC_USB3PHY_PHY_BCR 5
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#define GCC_USB_20_BCR 6
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#define GCC_USB_30_BCR 7
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
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#define GCC_MSS_RESTART 9
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#endif
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