mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 06:34:11 +08:00
6c0afb5039
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/clock.h
|
|
*
|
|
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
|
* Copyright (C) 2004-2011 Nokia Corporation
|
|
*
|
|
* Contacts:
|
|
* Richard Woodruff <r-woodruff2@ti.com>
|
|
* Paul Walmsley
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
|
|
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/list.h>
|
|
|
|
#include <linux/clkdev.h>
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/clk/ti.h>
|
|
|
|
/* struct clksel_rate.flags possibilities */
|
|
#define RATE_IN_242X (1 << 0)
|
|
#define RATE_IN_243X (1 << 1)
|
|
#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
|
|
#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
|
|
#define RATE_IN_36XX (1 << 4)
|
|
#define RATE_IN_4430 (1 << 5)
|
|
#define RATE_IN_TI816X (1 << 6)
|
|
#define RATE_IN_4460 (1 << 7)
|
|
#define RATE_IN_AM33XX (1 << 8)
|
|
#define RATE_IN_TI814X (1 << 9)
|
|
|
|
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
|
|
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
|
|
#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
|
|
#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
|
|
|
|
/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
|
|
#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
|
|
|
|
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
|
|
#define CORE_CLK_SRC_32K 0x0
|
|
#define CORE_CLK_SRC_DPLL 0x1
|
|
#define CORE_CLK_SRC_DPLL_X2 0x2
|
|
|
|
/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
|
|
#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
|
|
#define OMAP2XXX_EN_DPLL_LOCKED 0x3
|
|
|
|
/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
|
|
#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
|
|
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
|
|
|
|
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
|
|
#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
|
|
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
|
|
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
|
|
|
|
extern struct ti_clk_ll_ops omap_clk_ll_ops;
|
|
|
|
extern u16 cpu_mask;
|
|
|
|
extern const struct clkops clkops_omap2_dflt_wait;
|
|
extern const struct clkops clkops_omap2_dflt;
|
|
|
|
extern struct clk_functions omap2_clk_functions;
|
|
|
|
int __init omap2_clk_setup_ll_ops(void);
|
|
|
|
void __init ti_clk_init_features(void);
|
|
#endif
|