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424953cf3c
Now that SCM can be a loadable module, we have to add another dependency to avoid link failures when ipa or adreno-gpu are built-in: aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe': ipa_main.c:(.text+0xfc4): undefined reference to `qcom_scm_is_available' ld.lld: error: undefined symbol: qcom_scm_is_available >>> referenced by adreno_gpu.c >>> gpu/drm/msm/adreno/adreno_gpu.o:(adreno_zap_shader_load) in archive drivers/built-in.a This can happen when CONFIG_ARCH_QCOM is disabled and we don't select QCOM_MDT_LOADER, but some other module selects QCOM_SCM. Ideally we'd use a similar dependency here to what we have for QCOM_RPROC_COMMON, but that causes dependency loops from other things selecting QCOM_SCM. This appears to be an endless problem, so try something different this time: - CONFIG_QCOM_SCM becomes a hidden symbol that nothing 'depends on' but that is simply selected by all of its users - All the stubs in include/linux/qcom_scm.h can go away - arm-smccc.h needs to provide a stub for __arm_smccc_smc() to allow compile-testing QCOM_SCM on all architectures. - To avoid a circular dependency chain involving RESET_CONTROLLER and PINCTRL_SUNXI, drop the 'select RESET_CONTROLLER' statement. According to my testing this still builds fine, and the QCOM platform selects this symbol already. Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Alex Elder <elder@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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#include <linux/err.h>
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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u32 addr;
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u32 val;
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};
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struct qcom_scm_vmperm {
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int vmid;
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int perm;
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};
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enum qcom_scm_ocmem_client {
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QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
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QCOM_SCM_OCMEM_GRAPHICS_ID,
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QCOM_SCM_OCMEM_VIDEO_ID,
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QCOM_SCM_OCMEM_LP_AUDIO_ID,
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QCOM_SCM_OCMEM_SENSORS_ID,
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QCOM_SCM_OCMEM_OTHER_OS_ID,
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QCOM_SCM_OCMEM_DEBUG_ID,
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};
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enum qcom_scm_sec_dev_id {
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QCOM_SCM_MDSS_DEV_ID = 1,
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QCOM_SCM_OCMEM_DEV_ID = 5,
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QCOM_SCM_PCIE0_DEV_ID = 11,
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QCOM_SCM_PCIE1_DEV_ID = 12,
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QCOM_SCM_GFX_DEV_ID = 18,
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QCOM_SCM_UFS_DEV_ID = 19,
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QCOM_SCM_ICE_DEV_ID = 20,
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};
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enum qcom_scm_ice_cipher {
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QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
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QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
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QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
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QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
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};
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#define QCOM_SCM_VMID_HLOS 0x3
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#define QCOM_SCM_VMID_MSS_MSA 0xF
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#define QCOM_SCM_VMID_WLAN 0x18
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#define QCOM_SCM_VMID_WLAN_CE 0x19
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#define QCOM_SCM_PERM_READ 0x4
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#define QCOM_SCM_PERM_WRITE 0x2
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#define QCOM_SCM_PERM_EXEC 0x1
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#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
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#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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extern bool qcom_scm_is_available(void);
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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extern bool qcom_scm_restore_sec_cfg_available(void);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
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u32 cp_nonpixel_start,
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u32 cp_nonpixel_size);
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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extern bool qcom_scm_ocmem_lock_available(void);
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extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size, u32 mode);
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extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size);
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extern bool qcom_scm_ice_available(void);
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extern int qcom_scm_ice_invalidate_key(u32 index);
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extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
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enum qcom_scm_ice_cipher cipher,
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u32 data_unit_size);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
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u64 limit_node, u32 node_id, u64 version);
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extern int qcom_scm_lmh_profile_change(u32 profile_id);
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extern bool qcom_scm_lmh_dcvsh_available(void);
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#endif
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