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7999d8d7a6
RETINSTR is a left-over from the days when we had 26-bit and 32-bit CPU support integrated into the same tree. Since this is no longer the case, we can now remove RETINSTR. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
63 lines
1.2 KiB
ArmAsm
63 lines
1.2 KiB
ArmAsm
/*
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* linux/arch/arm/lib/delay.S
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*
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* Copyright (C) 1995, 1996 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/param.h>
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.text
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.LC0: .word loops_per_jiffy
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.LC1: .word (2199023*HZ)>>11
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/*
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* r0 <= 2000
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* lpj <= 0x01ffffff (max. 3355 bogomips)
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* HZ <= 1000
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*/
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ENTRY(__udelay)
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ldr r2, .LC1
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mul r0, r2, r0
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ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
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ldr r2, .LC0
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ldr r2, [r2] @ max = 0x01ffffff
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mov r0, r0, lsr #14 @ max = 0x0001ffff
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mov r2, r2, lsr #10 @ max = 0x00007fff
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mul r0, r2, r0 @ max = 2^32-1
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movs r0, r0, lsr #6
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moveq pc, lr
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/*
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* loops = r0 * HZ * loops_per_jiffy / 1000000
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*
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* Oh, if only we had a cycle counter...
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*/
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@ Delay routine
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ENTRY(__delay)
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subs r0, r0, #1
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#if 0
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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movls pc, lr
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subs r0, r0, #1
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#endif
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bhi __delay
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mov pc, lr
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