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651be3cb08
We only support breakpoint/watchpoint of length 1, 2, 4 and 8. If we can support other length as well, then user may watch more data with less number of watchpoints (provided hardware supports it). For example: if we have to watch only 4th, 5th and 6th byte from a 64 bit aligned address, we will have to use two slots to implement it currently. One slot will watch a half word at offset 4 and other a byte at offset 6. If we can have a watchpoint of length 3 then we can watch it with single slot as well. ARM64 hardware does support such functionality, therefore adding these new definitions in generic layer. Signed-off-by: Pratyush Anand <panand@redhat.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
35 lines
694 B
C
35 lines
694 B
C
#ifndef _UAPI_LINUX_HW_BREAKPOINT_H
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#define _UAPI_LINUX_HW_BREAKPOINT_H
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enum {
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HW_BREAKPOINT_LEN_1 = 1,
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HW_BREAKPOINT_LEN_2 = 2,
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HW_BREAKPOINT_LEN_3 = 3,
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HW_BREAKPOINT_LEN_4 = 4,
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HW_BREAKPOINT_LEN_5 = 5,
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HW_BREAKPOINT_LEN_6 = 6,
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HW_BREAKPOINT_LEN_7 = 7,
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HW_BREAKPOINT_LEN_8 = 8,
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};
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enum {
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HW_BREAKPOINT_EMPTY = 0,
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HW_BREAKPOINT_R = 1,
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HW_BREAKPOINT_W = 2,
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HW_BREAKPOINT_RW = HW_BREAKPOINT_R | HW_BREAKPOINT_W,
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HW_BREAKPOINT_X = 4,
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HW_BREAKPOINT_INVALID = HW_BREAKPOINT_RW | HW_BREAKPOINT_X,
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};
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enum bp_type_idx {
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TYPE_INST = 0,
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#ifdef CONFIG_HAVE_MIXED_BREAKPOINTS_REGS
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TYPE_DATA = 0,
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#else
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TYPE_DATA = 1,
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#endif
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TYPE_MAX
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};
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#endif /* _UAPI_LINUX_HW_BREAKPOINT_H */
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