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e17933c2c0
The l3 interconnect ip is same for OMAP4 and OMAP5. So reuse the l3 error handler error code for OMAP5 as well. Also a few targets has been newly added for OMAP5. So updating the driver for that here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
177 lines
3.7 KiB
C
177 lines
3.7 KiB
C
/*
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* OMAP4XXX L3 Interconnect error handling driver header
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*
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* Copyright (C) 2011 Texas Corporation
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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#define L3_MODULES 3
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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/* L3 TARG register offsets */
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#define L3_TARG_STDERRLOG_MAIN 0x48
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
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#define L3_TARG_STDERRLOG_MSTADDR 0x68
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#define L3_FLAGMUX_REGERR0 0xc
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#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
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static u32 l3_flagmux[L3_MODULES] = {
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0x500,
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0x1000,
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0X0200
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};
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/* L3 Target standard Error register offsets */
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static u32 l3_targ_inst_clk1[] = {
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0x100, /* DMM1 */
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0x200, /* DMM2 */
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0x300, /* ABE */
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0x400, /* L4CFG */
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0x600, /* CLK2 PWR DISC */
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0x0, /* Host CLK1 */
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0x900 /* L4 Wakeup */
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};
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static u32 l3_targ_inst_clk2[] = {
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0x500, /* CORTEX M3 */
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0x300, /* DSS */
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0x100, /* GPMC */
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0x400, /* ISS */
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0x700, /* IVAHD */
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0xD00, /* missing in TRM corresponds to AES1*/
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0x900, /* L4 PER0*/
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0x200, /* OCMRAM */
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0x100, /* missing in TRM corresponds to GPMC sERROR*/
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0x600, /* SGX */
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0x800, /* SL2 */
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0x1600, /* C2C */
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0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
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0xF00, /* missing in TRM corrsponds to SHA1*/
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0xE00, /* missing in TRM corresponds to AES2*/
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0xC00, /* L4 PER3 */
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0xA00, /* L4 PER1*/
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0xB00, /* L4 PER2*/
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0x0, /* HOST CLK2 */
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0x1800, /* CAL */
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0x1700 /* LLI */
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};
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static u32 l3_targ_inst_clk3[] = {
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0x0100 /* EMUSS */,
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0x0300, /* DEBUGSS_CT_TBR */
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0x0 /* HOST CLK3 */
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};
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static struct l3_masters_data {
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u32 id;
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char name[10];
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} l3_masters[] = {
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{ 0x0 , "MPU"},
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{ 0x10, "CS_ADP"},
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{ 0x14, "xxx"},
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{ 0x20, "DSP"},
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{ 0x30, "IVAHD"},
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{ 0x40, "ISS"},
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{ 0x44, "DucatiM3"},
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{ 0x48, "FaceDetect"},
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{ 0x50, "SDMA_Rd"},
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{ 0x54, "SDMA_Wr"},
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{ 0x58, "xxx"},
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{ 0x5C, "xxx"},
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{ 0x60, "SGX"},
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{ 0x70, "DSS"},
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{ 0x80, "C2C"},
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{ 0x88, "xxx"},
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{ 0x8C, "xxx"},
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{ 0x90, "HSI"},
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{ 0xA0, "MMC1"},
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{ 0xA4, "MMC2"},
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{ 0xA8, "MMC6"},
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{ 0xB0, "UNIPRO1"},
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{ 0xC0, "USBHOSTHS"},
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{ 0xC4, "USBOTGHS"},
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{ 0xC8, "USBHOSTFS"}
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};
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static char *l3_targ_inst_name[L3_MODULES][21] = {
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{
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"DMM1",
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"DMM2",
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"ABE",
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"L4CFG",
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"CLK2 PWR DISC",
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"HOST CLK1",
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"L4 WAKEUP"
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},
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{
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"CORTEX M3" ,
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"DSS ",
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"GPMC ",
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"ISS ",
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"IVAHD ",
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"AES1",
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"L4 PER0",
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"OCMRAM ",
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"GPMC sERROR",
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"SGX ",
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"SL2 ",
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"C2C ",
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"PWR DISC CLK1",
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"SHA1",
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"AES2",
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"L4 PER3",
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"L4 PER1",
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"L4 PER2",
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"HOST CLK2",
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"CAL",
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"LLI"
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},
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{
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"EMUSS",
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"DEBUG SOURCE",
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"HOST CLK3"
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},
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};
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static u32 *l3_targ[L3_MODULES] = {
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l3_targ_inst_clk1,
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l3_targ_inst_clk2,
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l3_targ_inst_clk3,
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};
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struct omap4_l3 {
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struct device *dev;
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struct clk *ick;
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/* memory base */
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void __iomem *l3_base[L3_MODULES];
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int debug_irq;
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int app_irq;
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};
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#endif
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