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https://github.com/edk2-porting/linux-next.git
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303fc0870f
Fix panic seen on some IBM and HP systems on 2.6.32-rc6: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<ffffffff8120bf3f>] find_next_bit+0x77/0x9c [...] [<ffffffff8120bbde>] cpumask_next_and+0x2e/0x3b [<ffffffff81225c62>] pci_device_probe+0x8e/0xf5 [<ffffffff812b9be6>] ? driver_sysfs_add+0x47/0x6c [<ffffffff812b9da5>] driver_probe_device+0xd9/0x1f9 [<ffffffff812b9f1d>] __driver_attach+0x58/0x7c [<ffffffff812b9ec5>] ? __driver_attach+0x0/0x7c [<ffffffff812b9298>] bus_for_each_dev+0x54/0x89 [<ffffffff812b9b4f>] driver_attach+0x19/0x1b [<ffffffff812b97ae>] bus_add_driver+0xd3/0x23d [<ffffffff812ba1e7>] driver_register+0x98/0x109 [<ffffffff81225ed0>] __pci_register_driver+0x63/0xd3 [<ffffffff81072776>] ? up_read+0x26/0x2a [<ffffffffa0081000>] ? k8temp_init+0x0/0x20 [k8temp] [<ffffffffa008101e>] k8temp_init+0x1e/0x20 [k8temp] [<ffffffff8100a073>] do_one_initcall+0x6d/0x185 [<ffffffff8108d765>] sys_init_module+0xd3/0x236 [<ffffffff81011ac2>] system_call_fastpath+0x16/0x1b I put in a printk and commented out the set_dev_node() call when and got this output: quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x0 quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x1 quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x2 quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x3 I.e. the issue appears to be that the HW has set val to a valid value, however, the system is only configured for a single node -- 0, the others are offline. Check to see if the node is actually online before setting the numa node for an AMD northbridge in quirk_amd_nb_node(). Signed-off-by: Prarit Bhargava <prarit@redhat.com> Cc: bhavna.sarathy@amd.com Cc: jbarnes@virtuousgeek.org Cc: andreas.herrmann3@amd.com LKML-Reference: <20091112180933.12532.98685.sendpatchset@prarit.bos.redhat.com> [ v2: clean up the code and add comments ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
540 lines
14 KiB
C
540 lines
14 KiB
C
/*
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* This file contains work-arounds for x86 and x86_64 platform bugs.
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/hpet.h>
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#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
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{
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u8 config, rev;
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u16 word;
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/* BIOS may enable hardware IRQ balancing for
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* E7520/E7320/E7525(revision ID 0x9 and below)
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* based platforms.
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* Disable SW irqbalance/affinity on those platforms.
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*/
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pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
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if (rev > 0x9)
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return;
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/* enable access to config space*/
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pci_read_config_byte(dev, 0xf4, &config);
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pci_write_config_byte(dev, 0xf4, config|0x2);
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/*
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* read xTPR register. We may not have a pci_dev for device 8
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* because it might be hidden until the above write.
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*/
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pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
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if (!(word & (1 << 13))) {
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dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
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"disabling irq balancing and affinity\n");
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noirqdebug_setup("");
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#ifdef CONFIG_PROC_FS
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no_irq_affinity = 1;
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#endif
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}
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/* put back the original value for config space*/
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if (!(config & 0x2))
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pci_write_config_byte(dev, 0xf4, config);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
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quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
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quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
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quirk_intel_irqbalance);
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#endif
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#if defined(CONFIG_HPET_TIMER)
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unsigned long force_hpet_address;
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static enum {
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NONE_FORCE_HPET_RESUME,
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OLD_ICH_FORCE_HPET_RESUME,
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ICH_FORCE_HPET_RESUME,
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VT8237_FORCE_HPET_RESUME,
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NVIDIA_FORCE_HPET_RESUME,
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ATI_FORCE_HPET_RESUME,
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} force_hpet_resume_type;
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static void __iomem *rcba_base;
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static void ich_force_hpet_resume(void)
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{
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u32 val;
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if (!force_hpet_address)
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return;
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BUG_ON(rcba_base == NULL);
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/* read the Function Disable register, dword mode only */
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80)) {
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/* HPET disabled in HPTC. Trying to enable */
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writel(val | 0x80, rcba_base + 0x3404);
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}
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80))
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BUG();
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else
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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return;
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}
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static void ich_force_enable_hpet(struct pci_dev *dev)
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{
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u32 val;
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u32 uninitialized_var(rcba);
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int err = 0;
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if (hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0xF0, &rcba);
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rcba &= 0xFFFFC000;
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if (rcba == 0) {
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dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
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"cannot force enable HPET\n");
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return;
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}
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/* use bits 31:14, 16 kB aligned */
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rcba_base = ioremap_nocache(rcba, 0x4000);
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if (rcba_base == NULL) {
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dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
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"cannot force enable HPET\n");
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return;
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}
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/* read the Function Disable register, dword mode only */
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val = readl(rcba_base + 0x3404);
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if (val & 0x80) {
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/* HPET is enabled in HPTC. Just not reported by BIOS */
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val = val & 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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"0x%lx\n", force_hpet_address);
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iounmap(rcba_base);
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return;
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}
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/* HPET disabled in HPTC. Trying to enable */
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writel(val | 0x80, rcba_base + 0x3404);
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80)) {
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err = 1;
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} else {
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val = val & 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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}
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if (err) {
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force_hpet_address = 0;
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iounmap(rcba_base);
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dev_printk(KERN_DEBUG, &dev->dev,
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"Failed to force enable HPET\n");
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} else {
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force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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"0x%lx\n", force_hpet_address);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
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ich_force_enable_hpet);
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static struct pci_dev *cached_dev;
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static void hpet_print_force_info(void)
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{
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printk(KERN_INFO "HPET not enabled in BIOS. "
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"You might try hpet=force boot option\n");
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}
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static void old_ich_force_hpet_resume(void)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (!force_hpet_address || !cached_dev)
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return;
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val == 0x4)
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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else
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BUG();
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}
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static void old_ich_force_enable_hpet(struct pci_dev *dev)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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/*
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* Bit 17 is HPET enable bit.
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* Bit 16:15 control the HPET base address.
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*/
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
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force_hpet_address);
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return;
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}
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/*
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* HPET is disabled. Trying enabling at FED00000 and check
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* whether it sticks
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*/
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(dev, 0xD0, gen_cntl);
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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/* HPET is enabled in HPTC. Just not reported by BIOS */
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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"0x%lx\n", force_hpet_address);
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cached_dev = dev;
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force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
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return;
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}
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dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
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}
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/*
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* Undocumented chipset features. Make sure that the user enforced
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* this.
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*/
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static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
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{
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if (hpet_force_user)
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old_ich_force_enable_hpet(dev);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
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old_ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
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old_ich_force_enable_hpet);
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static void vt8237_force_hpet_resume(void)
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{
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u32 val;
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if (!force_hpet_address || !cached_dev)
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return;
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val = 0xfed00000 | 0x80;
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pci_write_config_dword(cached_dev, 0x68, val);
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pci_read_config_dword(cached_dev, 0x68, &val);
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if (val & 0x80)
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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else
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BUG();
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}
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static void vt8237_force_enable_hpet(struct pci_dev *dev)
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{
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u32 uninitialized_var(val);
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if (hpet_address || force_hpet_address)
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return;
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if (!hpet_force_user) {
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hpet_print_force_info();
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return;
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}
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pci_read_config_dword(dev, 0x68, &val);
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/*
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* Bit 7 is HPET enable bit.
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* Bit 31:10 is HPET base address (contrary to what datasheet claims)
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*/
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if (val & 0x80) {
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force_hpet_address = (val & ~0x3ff);
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dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
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force_hpet_address);
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return;
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}
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/*
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* HPET is disabled. Trying enabling at FED00000 and check
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* whether it sticks
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*/
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val = 0xfed00000 | 0x80;
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pci_write_config_dword(dev, 0x68, val);
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pci_read_config_dword(dev, 0x68, &val);
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if (val & 0x80) {
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force_hpet_address = (val & ~0x3ff);
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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"0x%lx\n", force_hpet_address);
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cached_dev = dev;
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force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
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return;
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}
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dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
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vt8237_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
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vt8237_force_enable_hpet);
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static void ati_force_hpet_resume(void)
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{
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pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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}
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static u32 ati_ixp4x0_rev(struct pci_dev *dev)
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{
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u32 d;
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u8 b;
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pci_read_config_byte(dev, 0xac, &b);
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b &= ~(1<<5);
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pci_write_config_byte(dev, 0xac, b);
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pci_read_config_dword(dev, 0x70, &d);
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d |= 1<<8;
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pci_write_config_dword(dev, 0x70, d);
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pci_read_config_dword(dev, 0x8, &d);
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d &= 0xff;
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dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
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return d;
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}
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static void ati_force_enable_hpet(struct pci_dev *dev)
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{
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u32 d, val;
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u8 b;
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if (hpet_address || force_hpet_address)
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return;
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if (!hpet_force_user) {
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hpet_print_force_info();
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return;
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}
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d = ati_ixp4x0_rev(dev);
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if (d < 0x82)
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return;
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/* base address */
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pci_write_config_dword(dev, 0x14, 0xfed00000);
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pci_read_config_dword(dev, 0x14, &val);
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/* enable interrupt */
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outb(0x72, 0xcd6); b = inb(0xcd7);
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b |= 0x1;
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outb(0x72, 0xcd6); outb(b, 0xcd7);
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outb(0x72, 0xcd6); b = inb(0xcd7);
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if (!(b & 0x1))
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return;
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pci_read_config_dword(dev, 0x64, &d);
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d |= (1<<10);
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pci_write_config_dword(dev, 0x64, d);
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pci_read_config_dword(dev, 0x64, &d);
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if (!(d & (1<<10)))
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return;
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force_hpet_address = val;
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force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
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force_hpet_address);
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cached_dev = dev;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
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ati_force_enable_hpet);
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/*
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* Undocumented chipset feature taken from LinuxBIOS.
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*/
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static void nvidia_force_hpet_resume(void)
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{
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pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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}
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|
|
|
static void nvidia_force_enable_hpet(struct pci_dev *dev)
|
|
{
|
|
u32 uninitialized_var(val);
|
|
|
|
if (hpet_address || force_hpet_address)
|
|
return;
|
|
|
|
if (!hpet_force_user) {
|
|
hpet_print_force_info();
|
|
return;
|
|
}
|
|
|
|
pci_write_config_dword(dev, 0x44, 0xfed00001);
|
|
pci_read_config_dword(dev, 0x44, &val);
|
|
force_hpet_address = val & 0xfffffffe;
|
|
force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
|
|
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
|
|
force_hpet_address);
|
|
cached_dev = dev;
|
|
return;
|
|
}
|
|
|
|
/* ISA Bridges */
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
|
|
nvidia_force_enable_hpet);
|
|
|
|
/* LPC bridges */
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
|
|
nvidia_force_enable_hpet);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
|
|
nvidia_force_enable_hpet);
|
|
|
|
void force_hpet_resume(void)
|
|
{
|
|
switch (force_hpet_resume_type) {
|
|
case ICH_FORCE_HPET_RESUME:
|
|
ich_force_hpet_resume();
|
|
return;
|
|
case OLD_ICH_FORCE_HPET_RESUME:
|
|
old_ich_force_hpet_resume();
|
|
return;
|
|
case VT8237_FORCE_HPET_RESUME:
|
|
vt8237_force_hpet_resume();
|
|
return;
|
|
case NVIDIA_FORCE_HPET_RESUME:
|
|
nvidia_force_hpet_resume();
|
|
return;
|
|
case ATI_FORCE_HPET_RESUME:
|
|
ati_force_hpet_resume();
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
|
|
/* Set correct numa_node information for AMD NB functions */
|
|
static void __init quirk_amd_nb_node(struct pci_dev *dev)
|
|
{
|
|
struct pci_dev *nb_ht;
|
|
unsigned int devfn;
|
|
u32 node;
|
|
u32 val;
|
|
|
|
devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
|
|
nb_ht = pci_get_slot(dev->bus, devfn);
|
|
if (!nb_ht)
|
|
return;
|
|
|
|
pci_read_config_dword(nb_ht, 0x60, &val);
|
|
node = val & 7;
|
|
/*
|
|
* Some hardware may return an invalid node ID,
|
|
* so check it first:
|
|
*/
|
|
if (node_online(node))
|
|
set_dev_node(&dev->dev, node);
|
|
pci_dev_put(nb_ht);
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
|
|
quirk_amd_nb_node);
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
|
|
quirk_amd_nb_node);
|
|
#endif
|