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6a1fef6d00
With recent changes to the driver(switch to new cpdma layer),
the support for buffer descriptor address translation logic
is broken. This affects platforms where the physical address of
the descriptors as seen by the DMA engine is different from the
physical address.
Original Patch adding translation logic support:
Commit: ad021ae886
Signed-off-by: Sriramakrishnan A G <srk@ti.com>
Tested-By: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/*
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* Texas Instruments CPDMA Driver
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_CPDMA_H__
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#define __DAVINCI_CPDMA_H__
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#define CPDMA_MAX_CHANNELS BITS_PER_LONG
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#define tx_chan_num(chan) (chan)
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#define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS)
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#define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS)
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#define is_tx_chan(chan) (!is_rx_chan(chan))
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#define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1))
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#define chan_linear(chan) __chan_linear((chan)->chan_num)
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struct cpdma_params {
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struct device *dev;
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void __iomem *dmaregs;
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void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
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void __iomem *rxthresh, *rxfree;
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int num_chan;
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bool has_soft_reset;
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int min_packet_size;
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u32 desc_mem_phys;
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u32 desc_hw_addr;
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int desc_mem_size;
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int desc_align;
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/*
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* Some instances of embedded cpdma controllers have extra control and
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* status registers. The following flag enables access to these
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* "extended" registers.
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*/
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bool has_ext_regs;
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};
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struct cpdma_chan_stats {
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u32 head_enqueue;
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u32 tail_enqueue;
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u32 pad_enqueue;
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u32 misqueued;
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u32 desc_alloc_fail;
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u32 pad_alloc_fail;
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u32 runt_receive_buff;
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u32 runt_transmit_buff;
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u32 empty_dequeue;
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u32 busy_dequeue;
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u32 good_dequeue;
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u32 requeue;
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u32 teardown_dequeue;
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};
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struct cpdma_ctlr;
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struct cpdma_chan;
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typedef void (*cpdma_handler_fn)(void *token, int len, int status);
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
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int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr);
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struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
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cpdma_handler_fn handler);
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int cpdma_chan_destroy(struct cpdma_chan *chan);
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int cpdma_chan_start(struct cpdma_chan *chan);
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int cpdma_chan_stop(struct cpdma_chan *chan);
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int cpdma_chan_dump(struct cpdma_chan *chan);
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int cpdma_chan_get_stats(struct cpdma_chan *chan,
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struct cpdma_chan_stats *stats);
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int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
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int len, gfp_t gfp_mask);
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int cpdma_chan_process(struct cpdma_chan *chan, int quota);
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int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
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void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
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int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
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enum cpdma_control {
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CPDMA_CMD_IDLE, /* write-only */
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CPDMA_COPY_ERROR_FRAMES, /* read-write */
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CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
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CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
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CPDMA_TX_PRIO_FIXED, /* read-write */
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CPDMA_STAT_IDLE, /* read-only */
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CPDMA_STAT_TX_ERR_CHAN, /* read-only */
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CPDMA_STAT_TX_ERR_CODE, /* read-only */
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CPDMA_STAT_RX_ERR_CHAN, /* read-only */
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CPDMA_STAT_RX_ERR_CODE, /* read-only */
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CPDMA_RX_BUFFER_OFFSET, /* read-write */
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};
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int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
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int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
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#endif
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