mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 13:13:57 +08:00
de17c52002
PCI host drivers have already matched on compatible strings, so checking device_type is redundant. Also, device_type is considered deprecated for FDT though we've still been requiring it for PCI hosts as it is useful for finding PCI buses. Signed-off-by: Rob Herring <robh@kernel.org> [lorenzo.pieralisi@arm.com: reformatted the log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Alan Douglas <adouglas@cadence.com> Acked-by: Subrahmaya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Alan Douglas <adouglas@cadence.com> Cc: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Cc: Michal Simek <michal.simek@xilinx.com> Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org
862 lines
24 KiB
C
862 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Mobiveil PCIe Host controller
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*
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* Copyright (c) 2018 Mobiveil Inc.
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* Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../pci.h"
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/* register offsets and bit positions */
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/*
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* translation tables are grouped into windows, each window registers are
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* grouped into blocks of 4 or 16 registers each
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*/
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#define PAB_REG_BLOCK_SIZE 16
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#define PAB_EXT_REG_BLOCK_SIZE 4
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#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
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#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
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#define LTSSM_STATUS 0x0404
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#define LTSSM_STATUS_L0_MASK 0x3f
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#define LTSSM_STATUS_L0 0x2d
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#define PAB_CTRL 0x0808
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#define AMBA_PIO_ENABLE_SHIFT 0
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#define PEX_PIO_ENABLE_SHIFT 1
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#define PAGE_SEL_SHIFT 13
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#define PAGE_SEL_MASK 0x3f
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#define PAGE_LO_MASK 0x3ff
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#define PAGE_SEL_EN 0xc00
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#define PAGE_SEL_OFFSET_SHIFT 10
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#define PAB_AXI_PIO_CTRL 0x0840
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#define APIO_EN_MASK 0xf
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#define PAB_PEX_PIO_CTRL 0x08c0
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#define PIO_ENABLE_SHIFT 0
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#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
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#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
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#define PAB_INTP_INTX_MASK 0x01e0
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#define PAB_INTP_MSI_MASK 0x8
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#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
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#define WIN_ENABLE_SHIFT 0
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#define WIN_TYPE_SHIFT 1
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#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
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#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
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#define AXI_WINDOW_ALIGN_MASK 3
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#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
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#define PAB_BUS_SHIFT 24
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#define PAB_DEVICE_SHIFT 19
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#define PAB_FUNCTION_SHIFT 16
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#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
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#define PAB_INTP_AXI_PIO_CLASS 0x474
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#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
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#define AMAP_CTRL_EN_SHIFT 0
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#define AMAP_CTRL_TYPE_SHIFT 1
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#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
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#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
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#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
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#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
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/* starting offset of INTX bits in status register */
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#define PAB_INTX_START 5
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/* supported number of MSI interrupts */
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#define PCI_NUM_MSI 16
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/* MSI registers */
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#define MSI_BASE_LO_OFFSET 0x04
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#define MSI_BASE_HI_OFFSET 0x08
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#define MSI_SIZE_OFFSET 0x0c
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#define MSI_ENABLE_OFFSET 0x14
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#define MSI_STATUS_OFFSET 0x18
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#define MSI_DATA_OFFSET 0x20
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#define MSI_ADDR_L_OFFSET 0x24
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#define MSI_ADDR_H_OFFSET 0x28
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/* outbound and inbound window definitions */
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#define WIN_NUM_0 0
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#define WIN_NUM_1 1
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#define CFG_WINDOW_TYPE 0
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#define IO_WINDOW_TYPE 1
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#define MEM_WINDOW_TYPE 2
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#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
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#define MAX_PIO_WINDOWS 8
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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struct mobiveil_msi { /* MSI information */
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struct mutex lock; /* protect bitmap variable */
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struct irq_domain *msi_domain;
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struct irq_domain *dev_domain;
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phys_addr_t msi_pages_phys;
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int num_of_vectors;
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DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
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};
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struct mobiveil_pcie {
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struct platform_device *pdev;
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struct list_head resources;
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void __iomem *config_axi_slave_base; /* endpoint config base */
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void __iomem *csr_axi_slave_base; /* root port config base */
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void __iomem *apb_csr_base; /* MSI register base */
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phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
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struct irq_domain *intx_domain;
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raw_spinlock_t intx_mask_lock;
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int irq;
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int apio_wins;
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int ppio_wins;
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int ob_wins_configured; /* configured outbound windows */
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int ib_wins_configured; /* configured inbound windows */
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struct resource *ob_io_res;
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char root_bus_nr;
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struct mobiveil_msi msi;
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};
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static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
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const u32 reg)
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{
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writel_relaxed(value, pcie->csr_axi_slave_base + reg);
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}
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static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
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{
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return readl_relaxed(pcie->csr_axi_slave_base + reg);
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}
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static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
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{
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return (csr_readl(pcie, LTSSM_STATUS) &
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LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
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}
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static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct mobiveil_pcie *pcie = bus->sysdata;
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/* Only one device down on each root port */
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if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
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return false;
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/*
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* Do not read more than one device on the bus directly
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* attached to RC
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*/
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if ((bus->primary == pcie->root_bus_nr) && (devfn > 0))
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return false;
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return true;
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}
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/*
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* mobiveil_pcie_map_bus - routine to get the configuration base of either
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* root port or endpoint
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*/
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static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct mobiveil_pcie *pcie = bus->sysdata;
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if (!mobiveil_pcie_valid_device(bus, devfn))
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return NULL;
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if (bus->number == pcie->root_bus_nr) {
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/* RC config access */
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return pcie->csr_axi_slave_base + where;
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}
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/*
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* EP config access (in Config/APIO space)
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* Program PEX Address base (31..16 bits) with appropriate value
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* (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
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* Relies on pci_lock serialization
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*/
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csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
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PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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return pcie->config_axi_slave_base + where;
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}
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static struct pci_ops mobiveil_pcie_ops = {
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.map_bus = mobiveil_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static void mobiveil_pcie_isr(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
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struct device *dev = &pcie->pdev->dev;
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struct mobiveil_msi *msi = &pcie->msi;
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u32 msi_data, msi_addr_lo, msi_addr_hi;
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u32 intr_status, msi_status;
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unsigned long shifted_status;
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u32 bit, virq, val, mask;
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/*
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* The core provides a single interrupt for both INTx/MSI messages.
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* So we'll read both INTx and MSI status
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*/
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chained_irq_enter(chip, desc);
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/* read INTx status */
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val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
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mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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intr_status = val & mask;
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/* Handle INTx */
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if (intr_status & PAB_INTP_INTX_MASK) {
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shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
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PAB_INTX_START;
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do {
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
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virq = irq_find_mapping(pcie->intx_domain,
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bit + 1);
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if (virq)
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generic_handle_irq(virq);
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else
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dev_err_ratelimited(dev,
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"unexpected IRQ, INT%d\n", bit);
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/* clear interrupt */
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csr_writel(pcie,
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shifted_status << PAB_INTX_START,
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PAB_INTP_AMBA_MISC_STAT);
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}
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} while ((shifted_status >> PAB_INTX_START) != 0);
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}
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/* read extra MSI status register */
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msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
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/* handle MSI interrupts */
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while (msi_status & 1) {
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msi_data = readl_relaxed(pcie->apb_csr_base
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+ MSI_DATA_OFFSET);
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/*
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* MSI_STATUS_OFFSET register gets updated to zero
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* once we pop not only the MSI data but also address
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* from MSI hardware FIFO. So keeping these following
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* two dummy reads.
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*/
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msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_L_OFFSET);
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msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_H_OFFSET);
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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msi_data, msi_addr_hi, msi_addr_lo);
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virq = irq_find_mapping(msi->dev_domain, msi_data);
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if (virq)
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generic_handle_irq(virq);
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msi_status = readl_relaxed(pcie->apb_csr_base +
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MSI_STATUS_OFFSET);
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}
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/* Clear the interrupt status */
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csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
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chained_irq_exit(chip, desc);
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}
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static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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struct platform_device *pdev = pcie->pdev;
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struct device_node *node = dev->of_node;
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struct resource *res;
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/* map config resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"config_axi_slave");
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pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->config_axi_slave_base))
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return PTR_ERR(pcie->config_axi_slave_base);
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pcie->ob_io_res = res;
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/* map csr resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"csr_axi_slave");
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pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->csr_axi_slave_base))
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return PTR_ERR(pcie->csr_axi_slave_base);
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pcie->pcie_reg_base = res->start;
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/* map MSI config resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
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pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->apb_csr_base))
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return PTR_ERR(pcie->apb_csr_base);
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/* read the number of windows requested */
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if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
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pcie->apio_wins = MAX_PIO_WINDOWS;
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if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
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pcie->ppio_wins = MAX_PIO_WINDOWS;
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pcie->irq = platform_get_irq(pdev, 0);
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if (pcie->irq <= 0) {
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dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
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return -ENODEV;
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}
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irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
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return 0;
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}
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/*
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* select_paged_register - routine to access paged register of root complex
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*
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* registers of RC are paged, for this scheme to work
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* extracted higher 6 bits of the offset will be written to pg_sel
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* field of PAB_CTRL register and rest of the lower 10 bits enabled with
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* PAGE_SEL_EN are used as offset of the register.
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*/
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static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)
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{
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int pab_ctrl_dw, pg_sel;
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/* clear pg_sel field */
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pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);
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pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT));
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/* set pg_sel field */
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pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK;
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pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT));
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csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);
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}
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static void write_paged_register(struct mobiveil_pcie *pcie,
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u32 val, u32 offset)
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{
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u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
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select_paged_register(pcie, offset);
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csr_writel(pcie, val, off);
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}
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static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)
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{
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u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
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select_paged_register(pcie, offset);
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return csr_readl(pcie, off);
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}
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static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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int pci_addr, u32 type, u64 size)
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{
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int pio_ctrl_val;
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int amap_ctrl_dw;
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u64 size64 = ~(size - 1);
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if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
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dev_err(&pcie->pdev->dev,
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"ERROR: max inbound windows reached !\n");
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return;
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}
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pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
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csr_writel(pcie,
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pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
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amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));
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amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
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amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
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write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),
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PAB_PEX_AMAP_CTRL(win_num));
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write_paged_register(pcie, upper_32_bits(size64),
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PAB_EXT_PEX_AMAP_SIZEN(win_num));
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write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
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write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
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write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
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}
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/*
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* routine to program the outbound windows
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*/
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static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
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u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
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{
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u32 value, type;
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u64 size64 = ~(size - 1);
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if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
|
|
dev_err(&pcie->pdev->dev,
|
|
"ERROR: max outbound windows reached !\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
|
|
* to 4 KB in PAB_AXI_AMAP_CTRL register
|
|
*/
|
|
type = config_io_bit;
|
|
value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
|
|
csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
|
|
lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
|
|
|
|
write_paged_register(pcie, upper_32_bits(size64),
|
|
PAB_EXT_AXI_AMAP_SIZE(win_num));
|
|
|
|
/*
|
|
* program AXI window base with appropriate value in
|
|
* PAB_AXI_AMAP_AXI_WIN0 register
|
|
*/
|
|
value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
|
|
csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
|
|
PAB_AXI_AMAP_AXI_WIN(win_num));
|
|
|
|
value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
|
|
|
|
csr_writel(pcie, lower_32_bits(pci_addr),
|
|
PAB_AXI_AMAP_PEX_WIN_L(win_num));
|
|
csr_writel(pcie, upper_32_bits(pci_addr),
|
|
PAB_AXI_AMAP_PEX_WIN_H(win_num));
|
|
|
|
pcie->ob_wins_configured++;
|
|
}
|
|
|
|
static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
|
|
{
|
|
int retries;
|
|
|
|
/* check if the link is up or not */
|
|
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
|
|
if (mobiveil_pcie_link_up(pcie))
|
|
return 0;
|
|
|
|
usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
|
|
}
|
|
dev_err(&pcie->pdev->dev, "link never came up\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
|
|
{
|
|
phys_addr_t msg_addr = pcie->pcie_reg_base;
|
|
struct mobiveil_msi *msi = &pcie->msi;
|
|
|
|
pcie->msi.num_of_vectors = PCI_NUM_MSI;
|
|
msi->msi_pages_phys = (phys_addr_t)msg_addr;
|
|
|
|
writel_relaxed(lower_32_bits(msg_addr),
|
|
pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
|
|
writel_relaxed(upper_32_bits(msg_addr),
|
|
pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
|
|
writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
|
|
writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
|
|
}
|
|
|
|
static int mobiveil_host_init(struct mobiveil_pcie *pcie)
|
|
{
|
|
u32 value, pab_ctrl, type = 0;
|
|
int err;
|
|
struct resource_entry *win, *tmp;
|
|
|
|
err = mobiveil_bringup_link(pcie);
|
|
if (err) {
|
|
dev_info(&pcie->pdev->dev, "link bring-up failed\n");
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* program Bus Master Enable Bit in Command Register in PAB Config
|
|
* Space
|
|
*/
|
|
value = csr_readl(pcie, PCI_COMMAND);
|
|
csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER, PCI_COMMAND);
|
|
|
|
/*
|
|
* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
|
|
* register
|
|
*/
|
|
pab_ctrl = csr_readl(pcie, PAB_CTRL);
|
|
csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
|
|
(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
|
|
|
|
csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
|
|
PAB_INTP_AMBA_MISC_ENB);
|
|
|
|
/*
|
|
* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
|
|
* PAB_AXI_PIO_CTRL Register
|
|
*/
|
|
value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
|
|
csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
|
|
|
|
/*
|
|
* we'll program one outbound window for config reads and
|
|
* another default inbound window for all the upstream traffic
|
|
* rest of the outbound windows will be configured according to
|
|
* the "ranges" field defined in device tree
|
|
*/
|
|
|
|
/* config outbound translation window */
|
|
program_ob_windows(pcie, pcie->ob_wins_configured,
|
|
pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
|
|
resource_size(pcie->ob_io_res));
|
|
|
|
/* memory inbound translation window */
|
|
program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
|
|
|
|
/* Get the I/O and memory ranges from DT */
|
|
resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
|
|
type = 0;
|
|
if (resource_type(win->res) == IORESOURCE_MEM)
|
|
type = MEM_WINDOW_TYPE;
|
|
if (resource_type(win->res) == IORESOURCE_IO)
|
|
type = IO_WINDOW_TYPE;
|
|
if (type) {
|
|
/* configure outbound translation window */
|
|
program_ob_windows(pcie, pcie->ob_wins_configured,
|
|
win->res->start, 0, type,
|
|
resource_size(win->res));
|
|
}
|
|
}
|
|
|
|
/* setup MSI hardware registers */
|
|
mobiveil_pcie_enable_msi(pcie);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mobiveil_mask_intx_irq(struct irq_data *data)
|
|
{
|
|
struct irq_desc *desc = irq_to_desc(data->irq);
|
|
struct mobiveil_pcie *pcie;
|
|
unsigned long flags;
|
|
u32 mask, shifted_val;
|
|
|
|
pcie = irq_desc_get_chip_data(desc);
|
|
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
|
|
raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
|
|
shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
|
|
csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
|
|
raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
|
|
}
|
|
|
|
static void mobiveil_unmask_intx_irq(struct irq_data *data)
|
|
{
|
|
struct irq_desc *desc = irq_to_desc(data->irq);
|
|
struct mobiveil_pcie *pcie;
|
|
unsigned long flags;
|
|
u32 shifted_val, mask;
|
|
|
|
pcie = irq_desc_get_chip_data(desc);
|
|
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
|
|
raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
|
|
shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
|
|
csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
|
|
raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
|
|
}
|
|
|
|
static struct irq_chip intx_irq_chip = {
|
|
.name = "mobiveil_pcie:intx",
|
|
.irq_enable = mobiveil_unmask_intx_irq,
|
|
.irq_disable = mobiveil_mask_intx_irq,
|
|
.irq_mask = mobiveil_mask_intx_irq,
|
|
.irq_unmask = mobiveil_unmask_intx_irq,
|
|
};
|
|
|
|
/* routine to setup the INTx related data */
|
|
static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
|
|
irq_set_chip_data(irq, domain->host_data);
|
|
return 0;
|
|
}
|
|
|
|
/* INTx domain operations structure */
|
|
static const struct irq_domain_ops intx_domain_ops = {
|
|
.map = mobiveil_pcie_intx_map,
|
|
};
|
|
|
|
static struct irq_chip mobiveil_msi_irq_chip = {
|
|
.name = "Mobiveil PCIe MSI",
|
|
.irq_mask = pci_msi_mask_irq,
|
|
.irq_unmask = pci_msi_unmask_irq,
|
|
};
|
|
|
|
static struct msi_domain_info mobiveil_msi_domain_info = {
|
|
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
|
|
MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
|
|
.chip = &mobiveil_msi_irq_chip,
|
|
};
|
|
|
|
static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
|
{
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
|
|
phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
|
|
|
|
msg->address_lo = lower_32_bits(addr);
|
|
msg->address_hi = upper_32_bits(addr);
|
|
msg->data = data->hwirq;
|
|
|
|
dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
|
|
(int)data->hwirq, msg->address_hi, msg->address_lo);
|
|
}
|
|
|
|
static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
|
|
const struct cpumask *mask, bool force)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static struct irq_chip mobiveil_msi_bottom_irq_chip = {
|
|
.name = "Mobiveil MSI",
|
|
.irq_compose_msi_msg = mobiveil_compose_msi_msg,
|
|
.irq_set_affinity = mobiveil_msi_set_affinity,
|
|
};
|
|
|
|
static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
|
|
unsigned int virq, unsigned int nr_irqs, void *args)
|
|
{
|
|
struct mobiveil_pcie *pcie = domain->host_data;
|
|
struct mobiveil_msi *msi = &pcie->msi;
|
|
unsigned long bit;
|
|
|
|
WARN_ON(nr_irqs != 1);
|
|
mutex_lock(&msi->lock);
|
|
|
|
bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
|
|
if (bit >= msi->num_of_vectors) {
|
|
mutex_unlock(&msi->lock);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
set_bit(bit, msi->msi_irq_in_use);
|
|
|
|
mutex_unlock(&msi->lock);
|
|
|
|
irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
|
|
domain->host_data, handle_level_irq,
|
|
NULL, NULL);
|
|
return 0;
|
|
}
|
|
|
|
static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
|
|
unsigned int virq, unsigned int nr_irqs)
|
|
{
|
|
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
|
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
|
|
struct mobiveil_msi *msi = &pcie->msi;
|
|
|
|
mutex_lock(&msi->lock);
|
|
|
|
if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
|
|
dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
|
|
d->hwirq);
|
|
} else {
|
|
__clear_bit(d->hwirq, msi->msi_irq_in_use);
|
|
}
|
|
|
|
mutex_unlock(&msi->lock);
|
|
}
|
|
static const struct irq_domain_ops msi_domain_ops = {
|
|
.alloc = mobiveil_irq_msi_domain_alloc,
|
|
.free = mobiveil_irq_msi_domain_free,
|
|
};
|
|
|
|
static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
|
|
{
|
|
struct device *dev = &pcie->pdev->dev;
|
|
struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
|
|
struct mobiveil_msi *msi = &pcie->msi;
|
|
|
|
mutex_init(&pcie->msi.lock);
|
|
msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
|
|
&msi_domain_ops, pcie);
|
|
if (!msi->dev_domain) {
|
|
dev_err(dev, "failed to create IRQ domain\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
|
|
&mobiveil_msi_domain_info, msi->dev_domain);
|
|
if (!msi->msi_domain) {
|
|
dev_err(dev, "failed to create MSI domain\n");
|
|
irq_domain_remove(msi->dev_domain);
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
|
|
{
|
|
struct device *dev = &pcie->pdev->dev;
|
|
struct device_node *node = dev->of_node;
|
|
int ret;
|
|
|
|
/* setup INTx */
|
|
pcie->intx_domain = irq_domain_add_linear(node,
|
|
PCI_NUM_INTX, &intx_domain_ops, pcie);
|
|
|
|
if (!pcie->intx_domain) {
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
raw_spin_lock_init(&pcie->intx_mask_lock);
|
|
|
|
/* setup MSI */
|
|
ret = mobiveil_allocate_msi_domains(pcie);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mobiveil_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct mobiveil_pcie *pcie;
|
|
struct pci_bus *bus;
|
|
struct pci_bus *child;
|
|
struct pci_host_bridge *bridge;
|
|
struct device *dev = &pdev->dev;
|
|
resource_size_t iobase;
|
|
int ret;
|
|
|
|
/* allocate the PCIe port */
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
|
|
if (!bridge)
|
|
return -ENODEV;
|
|
|
|
pcie = pci_host_bridge_priv(bridge);
|
|
if (!pcie)
|
|
return -ENOMEM;
|
|
|
|
pcie->pdev = pdev;
|
|
|
|
ret = mobiveil_pcie_parse_dt(pcie);
|
|
if (ret) {
|
|
dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&pcie->resources);
|
|
|
|
/* parse the host bridge base addresses from the device tree file */
|
|
ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
|
|
&pcie->resources, &iobase);
|
|
if (ret) {
|
|
dev_err(dev, "Getting bridge resources failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/*
|
|
* configure all inbound and outbound windows and prepare the RC for
|
|
* config access
|
|
*/
|
|
ret = mobiveil_host_init(pcie);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize host\n");
|
|
goto error;
|
|
}
|
|
|
|
/* fixup for PCIe class register */
|
|
csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
|
|
|
|
/* initialize the IRQ domains */
|
|
ret = mobiveil_pcie_init_irq_domain(pcie);
|
|
if (ret) {
|
|
dev_err(dev, "Failed creating IRQ Domain\n");
|
|
goto error;
|
|
}
|
|
|
|
ret = devm_request_pci_bus_resources(dev, &pcie->resources);
|
|
if (ret)
|
|
goto error;
|
|
|
|
/* Initialize bridge */
|
|
list_splice_init(&pcie->resources, &bridge->windows);
|
|
bridge->dev.parent = dev;
|
|
bridge->sysdata = pcie;
|
|
bridge->busnr = pcie->root_bus_nr;
|
|
bridge->ops = &mobiveil_pcie_ops;
|
|
bridge->map_irq = of_irq_parse_and_map_pci;
|
|
bridge->swizzle_irq = pci_common_swizzle;
|
|
|
|
/* setup the kernel resources for the newly added PCIe root bus */
|
|
ret = pci_scan_root_bus_bridge(bridge);
|
|
if (ret)
|
|
goto error;
|
|
|
|
bus = bridge->bus;
|
|
|
|
pci_assign_unassigned_bus_resources(bus);
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
pci_bus_add_devices(bus);
|
|
|
|
return 0;
|
|
error:
|
|
pci_free_resource_list(&pcie->resources);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id mobiveil_pcie_of_match[] = {
|
|
{.compatible = "mbvl,gpex40-pcie",},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
|
|
|
|
static struct platform_driver mobiveil_pcie_driver = {
|
|
.probe = mobiveil_pcie_probe,
|
|
.driver = {
|
|
.name = "mobiveil-pcie",
|
|
.of_match_table = mobiveil_pcie_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver(mobiveil_pcie_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
|
|
MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
|