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0ec5a95bbb
This exposes the PB1176 ROM if you compile in the MTD physmap mapping and also the map_rom chiptype. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
84 lines
3.7 KiB
C
84 lines
3.7 KiB
C
/*
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* arch/arm/mach-realview/include/mach/board-pb1176.h
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*
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* Copyright (C) 2008 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_BOARD_PB1176_H
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#define __ASM_ARCH_BOARD_PB1176_H
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#include <mach/platform.h>
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/*
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* Peripheral addresses
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*/
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#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
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#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
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#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
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#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
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#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
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#define REALVIEW_PB1176_FLASH_BASE 0x30000000
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#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
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#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */
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#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M
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#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
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#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
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#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */
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#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */
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#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */
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#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */
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#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */
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#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */
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#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */
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#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */
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#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
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#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */
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#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */
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#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */
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/*
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* PCI regions
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*/
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#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */
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#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */
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#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */
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#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
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#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
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#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
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#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */
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#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
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#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
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#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
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#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
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#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
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#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */
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#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */
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#define REALVIEW_DC1176_ROM_BASE 0x10200000 /* 16KiB NRAM preudo-ROM, on devchip */
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#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
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#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
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#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
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/*
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* Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset
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*/
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#define REALVIEW_PB1176_SYS_SOFT_RESET 0x0100
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#endif /* __ASM_ARCH_BOARD_PB1176_H */
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