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299fad6b9b
These registers are only used in drivers/mfd/tmio_core.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* Copyright(c) 2009 Ian Molton <spyro@f2s.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/mfd/tmio.h>
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#define CNF_CMD 0x04
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#define CNF_CTL_BASE 0x10
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#define CNF_INT_PIN 0x3d
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#define CNF_STOP_CLK_CTL 0x40
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#define CNF_GCLK_CTL 0x41
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#define CNF_SD_CLK_MODE 0x42
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#define CNF_PIN_STATUS 0x44
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#define CNF_PWR_CTL_1 0x48
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#define CNF_PWR_CTL_2 0x49
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#define CNF_PWR_CTL_3 0x4a
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#define CNF_CARD_DETECT_MODE 0x4c
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#define CNF_SD_SLOT 0x50
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#define CNF_EXT_GCLK_CTL_1 0xf0
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#define CNF_EXT_GCLK_CTL_2 0xf1
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#define CNF_EXT_GCLK_CTL_3 0xf9
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#define CNF_SD_LED_EN_1 0xfa
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#define CNF_SD_LED_EN_2 0xfe
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#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base)
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{
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/* Enable the MMC/SD Control registers */
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sd_config_write16(cnf, shift, CNF_CMD, SDCREN);
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sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);
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/* Disable SD power during suspend */
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sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01);
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/* The below is required but why? FIXME */
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sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f);
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/* Power down SD bus */
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sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00);
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return 0;
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}
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EXPORT_SYMBOL(tmio_core_mmc_enable);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base)
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{
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/* Enable the MMC/SD Control registers */
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sd_config_write16(cnf, shift, CNF_CMD, SDCREN);
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sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);
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return 0;
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}
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EXPORT_SYMBOL(tmio_core_mmc_resume);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state)
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{
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sd_config_write8(cnf, shift, CNF_PWR_CTL_2, state ? 0x02 : 0x00);
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}
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EXPORT_SYMBOL(tmio_core_mmc_pwr);
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void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state)
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{
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sd_config_write8(cnf, shift, CNF_SD_CLK_MODE, state ? 1 : 0);
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}
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EXPORT_SYMBOL(tmio_core_mmc_clk_div);
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