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c6e6c96d8f
Add a new style driver for the clock control unit in Allwinner A31/A31s.
A few clocks are still missing:
- MIPI PLL's HDMI mode support
- EMAC clock
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
76 lines
1.1 KiB
Plaintext
76 lines
1.1 KiB
Plaintext
config SUNXI_CCU
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bool "Clock support for Allwinner SoCs"
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default ARCH_SUNXI
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if SUNXI_CCU
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# Base clock types
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config SUNXI_CCU_DIV
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bool
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select SUNXI_CCU_MUX
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config SUNXI_CCU_FRAC
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bool
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config SUNXI_CCU_GATE
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bool
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config SUNXI_CCU_MUX
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bool
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config SUNXI_CCU_PHASE
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bool
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# Multi-factor clocks
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config SUNXI_CCU_NK
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bool
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select SUNXI_CCU_GATE
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config SUNXI_CCU_NKM
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bool
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select RATIONAL
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select SUNXI_CCU_GATE
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config SUNXI_CCU_NKMP
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bool
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select RATIONAL
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select SUNXI_CCU_GATE
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config SUNXI_CCU_NM
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bool
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select RATIONAL
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select SUNXI_CCU_FRAC
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select SUNXI_CCU_GATE
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config SUNXI_CCU_MP
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bool
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select SUNXI_CCU_GATE
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select SUNXI_CCU_MUX
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# SoC Drivers
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config SUN6I_A31_CCU
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bool "Support for the Allwinner A31/A31s CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN6I
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config SUN8I_H3_CCU
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bool "Support for the Allwinner H3 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NKMP
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN8I
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endif
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