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65fddcfca8
The replacement of <asm/pgrable.h> with <linux/pgtable.h> made the include of the latter in the middle of asm includes. Fix this up with the aid of the below script and manual adjustments here and there. import sys import re if len(sys.argv) is not 3: print "USAGE: %s <file> <header>" % (sys.argv[0]) sys.exit(1) hdr_to_move="#include <linux/%s>" % sys.argv[2] moved = False in_hdrs = False with open(sys.argv[1], "r") as f: lines = f.readlines() for _line in lines: line = _line.rstrip(' ') if line == hdr_to_move: continue if line.startswith("#include <linux/"): in_hdrs = True elif not moved and in_hdrs: moved = True print hdr_to_move print line Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-4-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
614 lines
15 KiB
ArmAsm
614 lines
15 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
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*
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* Heavily based on proc-arm926.S
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* Maintainer: Assaf Hoffman <hoffman@marvell.com>
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.bss
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.align 3
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__cache_params_loc:
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.space 8
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.text
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__cache_params:
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.word __cache_params_loc
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mrc p15, 0, r0, c0, c0, 1 @ read cache type register
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ldr r1, __cache_params
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mov r2, #(16 << 5)
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tst r0, #(1 << 16) @ get way
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mov r0, r0, lsr #18 @ get cache size order
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movne r3, #((4 - 1) << 30) @ 4-way
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and r0, r0, #0xf
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moveq r3, #0 @ 1-way
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mov r2, r2, lsl r0 @ actual cache size
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movne r2, r2, lsr #2 @ turned into # of sets
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sub r2, r2, #(1 << 5)
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stmia r1, {r2, r3}
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ret lr
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/*
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* cpu_feroceon_proc_fin()
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*/
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ENTRY(cpu_feroceon_proc_fin)
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#if defined(CONFIG_CACHE_FEROCEON_L2) && \
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!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
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mov r0, #0
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mcr p15, 1, r0, c15, c9, 0 @ clean L2
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ret lr
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/*
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* cpu_feroceon_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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ret r0
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ENDPROC(cpu_feroceon_reset)
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.popsection
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/*
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* cpu_feroceon_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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ret lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(feroceon_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(feroceon_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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__flush_whole_cache:
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ldr r1, __cache_params
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ldmia r1, {r1, r3}
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1: orr ip, r1, r3
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2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
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subs ip, ip, #(1 << 30) @ next way
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bcs 2b
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subs r1, r1, #(1 << 5) @ next set
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bcs 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov r0, #0
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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.align 5
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ENTRY(feroceon_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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.align 5
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ENTRY(feroceon_range_flush_kern_dcache_area)
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mrs r2, cpsr
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add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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feroceon_dma_inv_range:
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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.align 5
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feroceon_range_dma_inv_range:
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mrs r2, cpsr
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c14, 0 @ D inv range start
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mcr p15, 5, r1, c15, c14, 1 @ D inv range top
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msr cpsr_c, r2 @ restore interrupts
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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feroceon_dma_clean_range:
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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.align 5
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feroceon_range_dma_clean_range:
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c13, 0 @ D clean range start
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mcr p15, 5, r1, c15, c13, 1 @ D clean range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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.align 5
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ENTRY(feroceon_range_dma_flush_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq feroceon_dma_clean_range
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bcs feroceon_dma_inv_range
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b feroceon_dma_flush_range
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ENDPROC(feroceon_dma_map_area)
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_range_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq feroceon_range_dma_clean_range
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bcs feroceon_range_dma_inv_range
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b feroceon_range_dma_flush_range
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ENDPROC(feroceon_range_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_dma_unmap_area)
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ret lr
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ENDPROC(feroceon_dma_unmap_area)
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.globl feroceon_flush_kern_cache_louis
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.equ feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions feroceon
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.macro range_alias basename
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.globl feroceon_range_\basename
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.type feroceon_range_\basename , %function
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.equ feroceon_range_\basename , feroceon_\basename
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.endm
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/*
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* Most of the cache functions are unchanged for this case.
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* Export suitable alias symbols for the unchanged functions:
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*/
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range_alias flush_icache_all
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range_alias flush_user_cache_all
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range_alias flush_kern_cache_all
|
|
range_alias flush_kern_cache_louis
|
|
range_alias flush_user_cache_range
|
|
range_alias coherent_kern_range
|
|
range_alias coherent_user_range
|
|
range_alias dma_unmap_area
|
|
|
|
define_cache_functions feroceon_range
|
|
|
|
.align 5
|
|
ENTRY(cpu_feroceon_dcache_clean_area)
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
mov r2, r0
|
|
mov r3, r1
|
|
#endif
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
add r0, r0, #CACHE_DLINESIZE
|
|
subs r1, r1, #CACHE_DLINESIZE
|
|
bhi 1b
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
|
|
add r2, r2, #CACHE_DLINESIZE
|
|
subs r3, r3, #CACHE_DLINESIZE
|
|
bhi 1b
|
|
#endif
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
|
ret lr
|
|
|
|
/* =============================== PageTable ============================== */
|
|
|
|
/*
|
|
* cpu_feroceon_switch_mm(pgd)
|
|
*
|
|
* Set the translation base pointer to be as described by pgd.
|
|
*
|
|
* pgd: new page tables
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_feroceon_switch_mm)
|
|
#ifdef CONFIG_MMU
|
|
/*
|
|
* Note: we wish to call __flush_whole_cache but we need to preserve
|
|
* lr to do so. The only way without touching main memory is to
|
|
* use r2 which is normally used to test the VM_EXEC flag, and
|
|
* compensate locally for the skipped ops if it is not set.
|
|
*/
|
|
mov r2, lr @ abuse r2 to preserve lr
|
|
bl __flush_whole_cache
|
|
@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
|
|
tst r2, #VM_EXEC
|
|
mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
|
mcreq p15, 0, ip, c7, c10, 4 @ drain WB
|
|
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
|
ret r2
|
|
#else
|
|
ret lr
|
|
#endif
|
|
|
|
/*
|
|
* cpu_feroceon_set_pte_ext(ptep, pte, ext)
|
|
*
|
|
* Set a PTE and flush it out
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_feroceon_set_pte_ext)
|
|
#ifdef CONFIG_MMU
|
|
armv3_set_pte_ext wc_disable=0
|
|
mov r0, r0
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
|
|
#endif
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
|
#endif
|
|
ret lr
|
|
|
|
/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
|
|
.globl cpu_feroceon_suspend_size
|
|
.equ cpu_feroceon_suspend_size, 4 * 3
|
|
#ifdef CONFIG_ARM_CPU_SUSPEND
|
|
ENTRY(cpu_feroceon_do_suspend)
|
|
stmfd sp!, {r4 - r6, lr}
|
|
mrc p15, 0, r4, c13, c0, 0 @ PID
|
|
mrc p15, 0, r5, c3, c0, 0 @ Domain ID
|
|
mrc p15, 0, r6, c1, c0, 0 @ Control register
|
|
stmia r0, {r4 - r6}
|
|
ldmfd sp!, {r4 - r6, pc}
|
|
ENDPROC(cpu_feroceon_do_suspend)
|
|
|
|
ENTRY(cpu_feroceon_do_resume)
|
|
mov ip, #0
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
|
|
ldmia r0, {r4 - r6}
|
|
mcr p15, 0, r4, c13, c0, 0 @ PID
|
|
mcr p15, 0, r5, c3, c0, 0 @ Domain ID
|
|
mcr p15, 0, r1, c2, c0, 0 @ TTB address
|
|
mov r0, r6 @ control register
|
|
b cpu_resume_mmu
|
|
ENDPROC(cpu_feroceon_do_resume)
|
|
#endif
|
|
|
|
.type __feroceon_setup, #function
|
|
__feroceon_setup:
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
|
#ifdef CONFIG_MMU
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
|
#endif
|
|
|
|
adr r5, feroceon_crval
|
|
ldmia r5, {r5, r6}
|
|
mrc p15, 0, r0, c1, c0 @ get control register v4
|
|
bic r0, r0, r5
|
|
orr r0, r0, r6
|
|
ret lr
|
|
.size __feroceon_setup, . - __feroceon_setup
|
|
|
|
/*
|
|
* B
|
|
* R P
|
|
* .RVI UFRS BLDP WCAM
|
|
* .011 .001 ..11 0101
|
|
*
|
|
*/
|
|
.type feroceon_crval, #object
|
|
feroceon_crval:
|
|
crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
|
|
|
|
__INITDATA
|
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
define_processor_functions feroceon, dabort=v5t_early_abort, pabort=legacy_pabort
|
|
|
|
.section ".rodata"
|
|
|
|
string cpu_arch_name, "armv5te"
|
|
string cpu_elf_name, "v5"
|
|
string cpu_feroceon_name, "Feroceon"
|
|
string cpu_88fr531_name, "Feroceon 88FR531-vd"
|
|
string cpu_88fr571_name, "Feroceon 88FR571-vd"
|
|
string cpu_88fr131_name, "Feroceon 88FR131"
|
|
|
|
.align
|
|
|
|
.section ".proc.info.init", "a"
|
|
|
|
.macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
|
|
.type __\name\()_proc_info,#object
|
|
__\name\()_proc_info:
|
|
.long \cpu_val
|
|
.long \cpu_mask
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
initfn __feroceon_setup, __\name\()_proc_info
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long \cpu_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long \cache
|
|
.size __\name\()_proc_info, . - __\name\()_proc_info
|
|
.endm
|
|
|
|
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
|
|
feroceon_proc_info feroceon_old_id, 0x41009260, 0xff00fff0, \
|
|
cpu_name=cpu_feroceon_name, cache=feroceon_cache_fns
|
|
#endif
|
|
|
|
feroceon_proc_info 88fr531, 0x56055310, 0xfffffff0, cpu_88fr531_name, \
|
|
cache=feroceon_cache_fns
|
|
feroceon_proc_info 88fr571, 0x56155710, 0xfffffff0, cpu_88fr571_name, \
|
|
cache=feroceon_range_cache_fns
|
|
feroceon_proc_info 88fr131, 0x56251310, 0xfffffff0, cpu_88fr131_name, \
|
|
cache=feroceon_range_cache_fns
|