mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 13:43:55 +08:00
2bedea8f26
This patch removes the bcma_core_pci_power_save() call from
the bcma_core_pci_{up,down}() functions as it tries to schedule
thus requiring to call them from non-atomic context. The function
bcma_core_pci_power_save() is now exported so the calling module
can explicitly use it in non-atomic context. This fixes the
'scheduling while atomic' issue reported by Tod Jackson and
Joe Perches.
[ 13.210710] BUG: scheduling while atomic: dhcpcd/1800/0x00000202
[ 13.210718] Modules linked in: brcmsmac nouveau coretemp kvm_intel kvm cordic brcmutil bcma dell_wmi atl1c ttm mxm_wmi wmi
[ 13.210756] CPU: 2 PID: 1800 Comm: dhcpcd Not tainted 3.11.0-wl #1
[ 13.210762] Hardware name: Alienware M11x R2/M11x R2, BIOS A04 11/23/2010
[ 13.210767] ffff880177c92c40 ffff880170fd1948 ffffffff8169af5b 0000000000000007
[ 13.210777] ffff880170fd1ab0 ffff880170fd1958 ffffffff81697ee2 ffff880170fd19d8
[ 13.210785] ffffffff816a19f5 00000000000f4240 000000000000d080 ffff880170fd1fd8
[ 13.210794] Call Trace:
[ 13.210813] [<ffffffff8169af5b>] dump_stack+0x4f/0x84
[ 13.210826] [<ffffffff81697ee2>] __schedule_bug+0x43/0x51
[ 13.210837] [<ffffffff816a19f5>] __schedule+0x6e5/0x810
[ 13.210845] [<ffffffff816a1c34>] schedule+0x24/0x70
[ 13.210855] [<ffffffff816a04fc>] schedule_hrtimeout_range_clock+0x10c/0x150
[ 13.210867] [<ffffffff810684e0>] ? update_rmtp+0x60/0x60
[ 13.210877] [<ffffffff8106915f>] ? hrtimer_start_range_ns+0xf/0x20
[ 13.210887] [<ffffffff816a054e>] schedule_hrtimeout_range+0xe/0x10
[ 13.210897] [<ffffffff8104f6fb>] usleep_range+0x3b/0x40
[ 13.210910] [<ffffffffa00371af>] bcma_pcie_mdio_set_phy.isra.3+0x4f/0x80 [bcma]
[ 13.210921] [<ffffffffa003729f>] bcma_pcie_mdio_write.isra.4+0xbf/0xd0 [bcma]
[ 13.210932] [<ffffffffa0037498>] bcma_pcie_mdio_writeread.isra.6.constprop.13+0x18/0x30 [bcma]
[ 13.210942] [<ffffffffa00374ee>] bcma_core_pci_power_save+0x3e/0x80 [bcma]
[ 13.210953] [<ffffffffa003765d>] bcma_core_pci_up+0x2d/0x60 [bcma]
[ 13.210975] [<ffffffffa03dc17c>] brcms_c_up+0xfc/0x430 [brcmsmac]
[ 13.210989] [<ffffffffa03d1a7d>] brcms_up+0x1d/0x20 [brcmsmac]
[ 13.211003] [<ffffffffa03d2498>] brcms_ops_start+0x298/0x340 [brcmsmac]
[ 13.211020] [<ffffffff81600a12>] ? cfg80211_netdev_notifier_call+0xd2/0x5f0
[ 13.211030] [<ffffffff815fa53d>] ? packet_notifier+0xad/0x1d0
[ 13.211064] [<ffffffff81656e75>] ieee80211_do_open+0x325/0xf80
[ 13.211076] [<ffffffff8106ac09>] ? __raw_notifier_call_chain+0x9/0x10
[ 13.211086] [<ffffffff81657b41>] ieee80211_open+0x71/0x80
[ 13.211101] [<ffffffff81526267>] __dev_open+0x87/0xe0
[ 13.211109] [<ffffffff8152650c>] __dev_change_flags+0x9c/0x180
[ 13.211117] [<ffffffff815266a3>] dev_change_flags+0x23/0x70
[ 13.211127] [<ffffffff8158cd68>] devinet_ioctl+0x5b8/0x6a0
[ 13.211136] [<ffffffff8158d5c5>] inet_ioctl+0x75/0x90
[ 13.211147] [<ffffffff8150b38b>] sock_do_ioctl+0x2b/0x70
[ 13.211155] [<ffffffff8150b681>] sock_ioctl+0x71/0x2a0
[ 13.211169] [<ffffffff8114ed47>] do_vfs_ioctl+0x87/0x520
[ 13.211180] [<ffffffff8113f159>] ? ____fput+0x9/0x10
[ 13.211198] [<ffffffff8106228c>] ? task_work_run+0x9c/0xd0
[ 13.211202] [<ffffffff8114f271>] SyS_ioctl+0x91/0xb0
[ 13.211208] [<ffffffff816aa252>] system_call_fastpath+0x16/0x1b
[ 13.211217] NOHZ: local_softirq_pending 202
The issue was introduced in v3.11 kernel by following commit:
commit aa51e598d0
Author: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat Aug 24 00:32:31 2013 +0200
brcmsmac: use bcma PCIe up and down functions
replace the calls to bcma_core_pci_extend_L1timer() by calls to the
newly introduced bcma_core_pci_ip() and bcma_core_pci_down()
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This fix has been discussed with Hauke Mehrtens [1] selection
option 3) and is intended for v3.12.
Ref:
[1] http://mid.gmane.org/5239B12D.3040206@hauke-m.de
Cc: <stable@vger.kernel.org> # 3.11.x
Cc: Tod Jackson <tod.jackson@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Rafal Milecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
251 lines
13 KiB
C
251 lines
13 KiB
C
#ifndef LINUX_BCMA_DRIVER_PCI_H_
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#define LINUX_BCMA_DRIVER_PCI_H_
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#include <linux/types.h>
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struct pci_dev;
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/** PCI core registers. **/
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#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
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#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
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#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
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#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
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#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
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#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
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#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
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#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
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#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
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#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
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#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
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#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
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#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
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#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
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#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
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#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
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#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
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#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
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#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
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#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
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#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
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#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
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#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
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#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
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#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
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#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
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#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
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#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
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#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
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#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
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#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
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#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
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#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
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#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
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#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
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#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
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#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
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#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
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#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
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#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
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#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
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#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
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#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
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#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
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#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
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#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
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#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
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#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
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#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
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#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
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#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
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#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
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#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
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#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
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#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
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#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
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#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
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#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
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#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
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#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
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#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
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#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
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#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
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#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
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#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
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#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
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#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
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#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
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#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
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#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
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#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
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#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
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#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
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#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
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#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
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#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
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#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
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#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
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#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
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#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
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#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
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#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
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#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
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#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
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#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
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#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
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#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
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#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
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/* SBtoPCIx */
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#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
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#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
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#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
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#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
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#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
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#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
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#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
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#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
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#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
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#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
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#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
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/* PCIE protocol PHY diagnostic registers */
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#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
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#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
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#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
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#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
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#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
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#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
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#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
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#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
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#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
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#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
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#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
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#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
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#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
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#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
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#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
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#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
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#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
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/* PCIE protocol DLLP diagnostic registers */
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#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
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#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
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#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
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#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
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#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
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#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
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#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
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#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
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#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
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#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
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#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
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#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
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#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
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#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
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#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
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#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
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#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
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#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
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#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
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#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
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#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
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#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
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#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
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#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
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/* SERDES RX registers */
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#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
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#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
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#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
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#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
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#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
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#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
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/* SERDES PLL registers */
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#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
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#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
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/* PCIcore specific boardflags */
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#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
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/* PCIE Config space accessing MACROS */
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#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
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#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
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#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
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#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
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#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
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#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
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#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
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#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
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#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
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#define BCMA_CORE_PCI_
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/* MDIO devices (SERDES modules) */
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#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
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#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
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#define BCMA_CORE_PCI_MDIO_BLK0 0x800
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#define BCMA_CORE_PCI_MDIO_BLK1 0x801
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#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
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#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
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#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
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#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
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#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
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#define BCMA_CORE_PCI_MDIO_BLK2 0x802
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#define BCMA_CORE_PCI_MDIO_BLK3 0x803
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#define BCMA_CORE_PCI_MDIO_BLK4 0x804
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#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
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#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
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#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
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#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
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/* PCIE Root Capability Register bits (Host mode only) */
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#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
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struct bcma_drv_pci;
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struct bcma_bus;
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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struct bcma_drv_pci_host {
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struct bcma_drv_pci *pdev;
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u32 host_cfg_addr;
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spinlock_t cfgspace_lock;
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struct pci_controller pci_controller;
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struct pci_ops pci_ops;
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struct resource mem_resource;
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struct resource io_resource;
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};
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#endif
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struct bcma_drv_pci {
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struct bcma_device *core;
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u8 setup_done:1;
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u8 hostmode:1;
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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struct bcma_drv_pci_host *host_controller;
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#endif
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};
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/* Register access */
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#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
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#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
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#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
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#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
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extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
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extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
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struct bcma_device *core, bool enable);
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extern void bcma_core_pci_up(struct bcma_bus *bus);
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extern void bcma_core_pci_down(struct bcma_bus *bus);
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extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
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extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
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extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
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#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
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