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868afce21f
At present the driver for the UIC (the embedded interrupt controller in 4xx chips) uses the handle_level_irq() flow handler. It turns out this does not correctly handle level triggered interrupts on the UIC. Specifically, acknowledging an irq on the UIC (i.e. clearing the relevant bit in UIC_SR) will have no effect for a level interrupt which is still asserted by the external device, even if the irq is already masked. Therefore, unlike handle_level_irq() we must ack the interrupt after invoking the ISR (which should cause the device to stop asserting the irq) instead of acking it when we mask it, before the ISR. This patch implements this change, in a new handle_uic_irq(), a customised irq flow handler for the UIC. For edge triggered interrupts, handle_uic_irq() still uses the old flow - we must ack edge triggered interrupt before the ISR not after, or we could miss a second event which occurred between invoking the ISR and acking the irq. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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.. | ||
qe_lib | ||
axonram.c | ||
commproc.c | ||
cpm2_common.c | ||
cpm2_pic.c | ||
cpm2_pic.h | ||
dart_iommu.c | ||
dart.h | ||
dcr-low.S | ||
dcr.c | ||
fsl_pci.c | ||
fsl_pci.h | ||
fsl_soc.c | ||
fsl_soc.h | ||
grackle.c | ||
i8259.c | ||
indirect_pci.c | ||
ipic.c | ||
ipic.h | ||
Makefile | ||
micropatch.c | ||
mmio_nvram.c | ||
mpc8xx_pic.c | ||
mpc8xx_pic.h | ||
mpic_msi.c | ||
mpic_u3msi.c | ||
mpic.c | ||
mpic.h | ||
mv64x60_dev.c | ||
mv64x60_pci.c | ||
mv64x60_pic.c | ||
mv64x60.h | ||
pmi.c | ||
rtc_cmos_setup.c | ||
timer.c | ||
tsi108_dev.c | ||
tsi108_pci.c | ||
uic.c |