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82 lines
3.0 KiB
C
82 lines
3.0 KiB
C
#ifndef __ASM_SH_RENESAS_SDK7780_H
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#define __ASM_SH_RENESAS_SDK7780_H
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/*
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* linux/include/asm-sh/sdk7780.h
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*
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* Renesas Solutions SH7780 SDK Support
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* Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <asm/addrspace.h>
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/* Box specific addresses. */
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#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
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#define PA_ROM 0xa0000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_FROM 0xa0800000 /* Flash-ROM */
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#define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
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#define PA_EXT1 0xa4000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
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#define PA_SDRAM_SIZE 0x08000000
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#define PA_EXT4 0xb0000000
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#define PA_EXT4_SIZE 0x04000000
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#define PA_EXT_USER PA_EXT4 /* User Expansion Space */
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#define PA_PERIPHERAL PA_AREA5_IO
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/* SRAM/Reserved */
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#define PA_RESERVED (PA_PERIPHERAL + 0)
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/* FPGA base address */
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#define PA_FPGA (PA_PERIPHERAL + 0x01000000)
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/* SMC LAN91C111 */
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#define PA_LAN (PA_PERIPHERAL + 0x01800000)
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#define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
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#define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
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#define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
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#define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
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#define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
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#define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
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#define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
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#define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
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#define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */
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#define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */
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#define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */
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#define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */
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#define PA_LED FPGA_SLEDR
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#define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */
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#define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
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#define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
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#define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
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#define FPGA_EASR (PA_FPGA + 0x110) /* External area select */
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#define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */
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#define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */
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#define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */
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#define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */
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#define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */
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#define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */
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#define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */
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#define SDK7780_NR_IRL 15
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/* IDE/ATA interrupt */
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#define IRQ_CFCARD 14
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/* SMC interrupt */
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#define IRQ_ETHERNET 6
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/* arch/sh/boards/renesas/sdk7780/irq.c */
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void init_sdk7780_IRQ(void);
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#define __IO_PREFIX sdk7780
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_RENESAS_SDK7780_H */
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