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https://github.com/edk2-porting/linux-next.git
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b4626a7f48
This patch adds clock support to Loongson1C SoC. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Acked-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/*
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* Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <loongson1.h>
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#include "clk.h"
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#define OSC (24 * 1000000)
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#define DIV_APB 1
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static DEFINE_SPINLOCK(_lock);
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static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 pll, rate;
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pll = __raw_readl(LS1X_CLK_PLL_FREQ);
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rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
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rate *= OSC;
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rate >>= 2;
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return rate;
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}
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static const struct clk_ops ls1x_pll_clk_ops = {
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.recalc_rate = ls1x_pll_recalc_rate,
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};
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static const struct clk_div_table ahb_div_table[] = {
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[0] = { .val = 0, .div = 2 },
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[1] = { .val = 1, .div = 4 },
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[2] = { .val = 2, .div = 3 },
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[3] = { .val = 3, .div = 3 },
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};
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void __init ls1x_clk_init(void)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
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clk_hw_register_clkdev(hw, "osc_clk", NULL);
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/* clock derived from 24 MHz OSC clk */
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hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
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&ls1x_pll_clk_ops, 0);
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clk_hw_register_clkdev(hw, "pll_clk", NULL);
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hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
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CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
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DIV_CPU_SHIFT, DIV_CPU_WIDTH,
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CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ROUND_CLOSEST, &_lock);
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clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
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hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
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0, 1, 1);
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clk_hw_register_clkdev(hw, "cpu_clk", NULL);
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hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
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0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
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DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
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clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
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hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
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0, 1, 1);
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clk_hw_register_clkdev(hw, "dc_clk", NULL);
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hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
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0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
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DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
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ahb_div_table, &_lock);
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clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
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hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
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0, 1, 1);
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clk_hw_register_clkdev(hw, "ahb_clk", NULL);
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clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
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clk_hw_register_clkdev(hw, "stmmaceth", NULL);
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/* clock derived from AHB clk */
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hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
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DIV_APB);
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clk_hw_register_clkdev(hw, "apb_clk", NULL);
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clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
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clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
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clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
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clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
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clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
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clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
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clk_hw_register_clkdev(hw, "serial8250", NULL);
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}
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