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989feafb84
With most of the clock code under clock driver already, the low-level register access code, and the init code for the same, is no longer needed outside the clock driver. Thus, these can be moved under clock driver also. Signed-off-by: Tero Kristo <t-kristo@ti.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.h
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2011 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
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#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
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#define RATE_IN_36XX (1 << 4)
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#define RATE_IN_4430 (1 << 5)
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#define RATE_IN_TI816X (1 << 6)
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#define RATE_IN_4460 (1 << 7)
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#define RATE_IN_AM33XX (1 << 8)
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#define RATE_IN_TI814X (1 << 9)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
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#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
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#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
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/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
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#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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#define CORE_CLK_SRC_DPLL_X2 0x2
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/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
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#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
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#define OMAP2XXX_EN_DPLL_LOCKED 0x3
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/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name);
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extern u16 cpu_mask;
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_omap2_dflt;
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extern struct clk_functions omap2_clk_functions;
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int __init omap2_clk_setup_ll_ops(void);
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void __init ti_clk_init_features(void);
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#endif
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